Meng-Fan Chang

A Low-Power Electronic Nose Signal-Processing Chip for a Portable Artificial Olfaction System

The bulkiness of current electronic nose (E-Nose) systems severely limits their portability. This study designed and fabricated an E-Nose signal-processing chip by using TSMC 0.18-μ m 1P6M complementary metal-oxide semiconductor technology to overcome the need to connect the device to a personal computer, which has traditionally been a major stumbling block in reducing the size of E-Nose systems. The proposed chip is based on a conductive polymer sensor array chip composed of multiwalled carbon nanotubes. The signal-processing chip comprises an interface circuit, an analog-to-digital converter, a memory module, and a microprocessor embedded with a pattern-recognition algorithm. Experimental results have verified the functionality of the proposed system, in which the E-Nose signal-processing chip successfully classified three odors, carbon tetrachloride (CCl4), chloroform (CHCl3), and 2-Butanone (MEK), demonstrating its potential for portable applications. The power consumption of this signal-processing chip was maintained at a very low 2.81 mW using a 1.8-V power supply, making it highly suitable for integration as an electronic nose system-on-chip.The bulkiness of current electronic nose (E-Nose) systems severely limits their portability. This study designed and fabricated an E-Nose signal-processing chip by using TSMC 0.18-μ m 1P6M complementary metal-oxide semiconductor technology to overcome the need to connect the device to a personal computer, which has traditionally been a major stumbling block in reducing the size of E-Nose systems. The proposed chip is based on a conductive polymer sensor array chip composed of multiwalled carbon nanotubes. The signal-processing chip comprises an interface circuit, an analog-to-digital converter, a memory module, and a microprocessor embedded with a pattern-recognition algorithm. Experimental results have verified the functionality of the proposed system, in which the E-Nose signal-processing chip successfully classified three odors, carbon tetrachloride (CCl4), chloroform (CHCl3), and 2-Butanone (MEK), demonstrating its potential for portable applications. The power consumption of this signal-processing chip was maintained at a very low 2.81 mW using a 1.8-V power supply, making it highly suitable for integration as an electronic nose system-on-chip.

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory

Decreasing read cell current (<i>I</i>_CELL) has become a major trend in nonvolatile memory (NVM). However, a reduced <i>I</i>_CELL leaves the operation of the sense amplifier (SAs) vulnerable to bitline (BL) level offset and SA input offset. Thus, small- <i>I</i>_CELL NVMs suffer from slow read speed or low read yield. In this study, we propose a new current-sampling-based SA (CSB-SA) to suppress the offset due to device mismatch, while maintaining tolerance for insufficient precharge time. These features enable CSB-SA to achieve a read speed 6.3 ×-8.1× faster than previous SAs, for sensing 100 nA <i>I</i>_CELLs on a 2 K-cell bitline. We fabricated a CMOS-logic-compatible, 90 nm, 512 Kb OTP macro, using the CSB-SA. This OTP macro achieves a random access time of 26 ns for reading sub-200 nA <i>I</i>_CELL. Measurements confirm that this 90 nm CSB-SA is also capable of sub-100 nA sensing.

A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme

Replica-cell sensing schemes are commonly used in the read circuits of flash memories to provide the appropriate reference current across various process, voltage and temperature (PVT) conditions. However, process variation on the replica array causes fluctuations in the settling time and the value of the reference current across dies or wafers, especially in split-gate flash memories. A long settling time of reference current slows down the access time, and causes ringing on outputs. Fluctuation in the reference current produces various sensing margins, and decreases the yield, due to tail bits. A circuit-level technique for embedded flash memories, called pre-stable current sensing (PSCS), is proposed to reduce the fluctuation in access time and sensing margin, without additional masks or process steps. Experiments on fabricated flash macros (4 Mb, 2 Mb, 1 Mb, and 512 Kb) using a 0.25 mum embedded flash process demonstrate that PSCS achieves uniform access time across hundreds of samples. Additionally, PSCS works with a wide range of supply voltages (1.1-3 V).

Wide

Voltage-dependent timing skews in precharge and sensing activities cause functional failure and reduce the speed of asynchronous static random-access memory (SRAM). Data-dependent bitline-leakage current further increases the timing skews and reduces the yield of asynchronous SRAM. A dual-mode self-timed (DMST) technique is developed for asynchronous SRAM to eliminate the timing-skew-induced failures and speed overhead across various process, voltage, and temperature conditions. The DMST technique employs a single replica column and new dummy cells to track both precharge and sensing activities in asynchronous SRAM, with bitline leakage considered. The DMST-technique simulation uses both 65-nm and 0.35-mum technologies. Several 0.35-mum DMST SRAM macros were fabricated in a test chip and embedded in a mass-produced system-on-a-chip suitable for various battery/supply-voltage configurations. Measurements demonstrated that the DMST technique can be operated continuously over a wide range of supply voltages, from 39.4% to 151.5% (or 212.1%, given device durability) of the nominal supply voltage (3.3 V). The fabricated macros also confirmed that the DMST technique is scalable for various bitline lengths and offers the same area overhead as conventional sense-tracking-only replica-column schemes.

V_{\rm DD}

Various input addresses and accessed code-patterns of a via-programming read only memory (ROM) cause substantial fluctuations in peak current and supply noise across cycles. This work analyzes the fluctuations in the supply noise that are associated with the pattern-dependent current profile of embedded via-programming ROM on a QFN package with various decoupling capacitances. A pattern-insensitive (PI) technique is developed for via-programming ROM to reduce both fluctuations of peak current and cycle current across various input addresses and accessed code-patterns. The PI technique involves the arranging of the data patterns of a ROM-code and the adjustment of the structures of row decoders and peripheral circuits. Experiments based on the designed test-setup on fabricated 0.25 mum 256 kb ROM macros demonstrate the fluctuation in peak current of conventional ROM and its reduction by the PI technique. The fluctuations of measured peak and cycle currents of PI-ROM are only 0.7% and 13.1% of those of conventional ROM. The PI-ROM also has a 94.5% lower standby current than conventional ROM.

Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems

Current-mode sense amplifiers (CSA) are commonly used in eNVM, because of their fast read speed at large bitline (BL) loads and small cell read currents. However, conventional CSAs are unable to achieve fast random read access time (TAC), due to significant summed input offsets (IOS-SUM) at read-path. This work proposes a calibration-based asymmetric-voltage-biased CSA (AVB-CSA) to suppress IOS-SUM and enable high-speed sensing without the need for run-time offset-cancellation operations. This work then fabricated two 90 nm AVB-CSA 1 Mb Flash testchips (with and without BL-length test-modes). The AVB-CSA eFlash macros with 512 rows achieved TAC of 3.9 ns at nominal VDD (1.2 V). The BL-length test-mode experiments confirmed a 1.53× improvement in TAC using AVB-CSA with a BL-length of 2048-rows operating at VDD=0.8 V.

Analysis and Reduction of Supply Noise Fluctuations Induced by Embedded Via-Programming ROM

Nonvolatile computing has been proven to be effective in dealing with power supply outages for on-chip check-pointing in emerging energy-harvesting Internet-of-Things applications. It also plays an important role in power-gating to cut off leakage power for higher energy efficiency. However, existing on-chip state backup solutions for D flip–flop (DFF) have a bottleneck of significant energy and/or latency penalties which limit the overall energy efficiency and computing progress. Meanwhile, these solutions rely on external control that limits compatibility and increases system complexity. This paper proposes an approach to fundamentally advancing the nonvolatile computing paradigm by intrinsically nonvolatile area-efficient latches and flip–flops designs using negative capacitance FET. These designs consume fJ-level energy and ns-level intrinsic latency for a backup plus restore operation, e.g., 2.4 fJ in energy and 1.1 ns in time for one proposed nonvolatile DFF with a supply power of 0.80 V.

An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros

Various code patterns of a via-programming read only memory (ROM) cause significant fluctuations in coupling noise between bitlines (BLs). This crosstalk between BLs leads to read failure in high-speed via-programmable ROMs and limits the coverage of applicable code patterns. This work presents a content-aware design framework (CADF) for via-programming ROMs to overcome the crosstalk induced read failure. The CADF ROMs employ a content-aware structure and correspondent code-structure programming algorithm to reduce the amount of coupling noise source while maintaining nonminimal BL load for crosstalk reduction. A 256-Kb conventional ROM and a 256-Kb CADF ROM were fabricated using a 0.25-mum logic CMOS process. The measured results ascertain that the read induced read failure is suppressed significantly by CADF. The CADF ROM also reduced 86.2% and 94.5% in power consumption and standby current compared to the conventional ROM, respectively

Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops

3D vertical-gate (3DVG) NAND flash is a promising candidate for next-generation high-density nonvolatile memory. Cross-layer process variation renders 3DVG NAND susceptible to decreased speeds, yield, and reliability. This can be attributed to (a) cross-layer mismatch in bitline capacitance (CBL), (b) the need for long program cycles, and (c) sensing-margin (SM) loss induced by the effects of background-pattern-dependency (BPD). This study proposes three circuit-level techniques to overcome these issues by employing the following: (1) distributed NAND-string scramble (DNSS), (2) layer-aware program-verify-and-read (LA-PV-R), and (3) a layer-aware-bitline-precharge (LA-BP) scheme. For an 8-layer 3DVG with 200 mV cross-layer mismatch in cell threshold voltage ( V THC), DNSS reduces the cross-layer C BL-mismatch by 41%, LA-PV-R using various program-threshold-voltages ( V THP) for each layer enables a 25% reduction in the number of program cycles, and LA-BP succeeds in reducing BPD-induced SM loss by 56%. A 2-layer 3DVG NAND testchip and 8-layer testkey were fabricated to evaluate the proposed methods. The LA-PV-R and LA-BP have achieved a 0.75 V difference in V THP between layer-0 and layer-1 with a 0.4V difference in BL clamping bias voltages and the LA-BP scheme has achieved a 44% reduction in BPD-induced SM loss. The three proposed schemes incur an area penalty of less than 0.1% in a Gb-scale 3DVG NAND device.

Crosstalk-insensitive via-programming ROMs using content-aware design framework

TSV-based 3D die-stacking technology enables the reuse of pre-designed, pre-tested logic dies stacked with multiple memory layers (NSTACK) in various configurations to form a universal-memory-capacity platform (UMCP). However, conventional 3D memories suffer speed, power and yield overheads due to the large parasitic load of TSV and cross-layer PVT variations when implemented in large NSTACK with wide IO, especially using via-last TSVs. This work proposes a semi-master-slave (SMS) memory structure with self-timed differential-TSV signal transfer (STDT) scheme to improve the speed, power, and yield of 3D memory devices, while providing high scalability in NSTACK for 3D-UMCP. The SMS scheme achieves the following: 1) a constant-load logic-SRAM interface across various NSTACK; 2) high tolerance for variations in cross-layer PVT, and 3) at-speed pre-bonding KGD sorting. The STDT scheme employs a TSV-load tracking scheme to achieve small TSV voltage swing for suppressing power and speed overheads of cross-layer TSV signal communication resulting from large TSV parasitic loads, particularly in UMCP designs with scalable NSTACK and wide-IO. To verify the viability of the proposed structure and scheme, we developed a 2-layer 32 kb 3D-SRAM testchip with layer-scalable test-modes using a via-last TSV process with die-to-die bonding. This testchip confirmed the functionality and demonstrated superior scalability in NSTACK with small speed overheads.