Chia-Hsin Wu

A world-band triple-mode 802.11a/b/g SOC in 0.13um CMOS

A world-band triple-mode SOC compliant with 802.11a/b/g is realized in 0.13 mum CMOS technology. This SOC features multiple integrated capless LDOs to be compatible with DC/DC supply for low current consumption and minimizing external BOMs. With supplying by a DC/DC converter, the measured 2.4 GHz/5 GHz sensitivity is -77.5 dBm/-74 dBm at 54 Mbps, and TX 2.4 GHz/5 GHz 54 Mbps EVM is -32 dB/-30 dB at an output power of -7 dBm/-8 dBm. This SOC consumes 71 mA/83 mA at RX mode and 56 mA/74 mA at TX mode at 2.4 GHz/5 GHz band respectively.

A 60nm WiFi/BT/GPS/FM combo connectivity SOC with integrated power amplifiers, virtual SP3T switch, and merged WiFi-BT transceiver

A highly integrated WiFi/BT/FM/GPS connectivity combo SOC is implemented in a 60nm CMOS process. This work presents the proposed WiFi/BT merged RF transceiver, a virtual SP3T switch, and DPD algorithm to save chip area, reduce BOM and enhance performance simultaneously. The WiFi/BT/FM/GPS RF transceiver areas are 1.7/1.3/0.8/1.0mm2, respectively. The measured WiFi 11g 54Mbps RX sensitivity is -78dBm and Pout is 20dBm with EVM of -28dB. The measured BT GMSK RX sensitivity is -94dBm and Pout is 10dBm. FM sensitivity is -110dBm and GPS cold/hot-start TTFF sensitivity is -148/-163dBm.

A 2×2 MIMO 802.11 abgn/ac WLAN SoC with integrated T/R switch and on-chip PA delivering VHT80 256QAM 17.5dBm in 55nm CMOS

This paper describes 2×2 MIMO 802.11ac Stage 1 WiFi + BT combo SoC chip with integrated dual-band PAs, LNAs, T/R switches, as well as a power management unit. The measured RX sensitivity of OFDM54M is -77.5dBm/ -77dBm in 2.4GHz and 5GHz, respectively. With the proposed broadband TX architecture, a high output power of 17.5dBm for 802.11ac Stage 1 VHT80 256QAM was achieved, and is extendable to the upcoming 802.11ac Stage2 VHT160. The maximum throughput achieved is 580Mbps in VHT80 MCS9 two-spatial stream mode, AWGN channel, with short GI. This chip occupies 27.8mm2 in 55nm 1P6M CMOS technology in which the MIMO WiFi RF and analog circuits occupies 7.7mm2.

A 70-Mb/s 100.5-dBm Sensitivity 65-nm LP MIMO Chipset for WiMAX Portable Router

In this paper, we present a low-power high-performance WiMAX chipset fully compliant with IEEE 802.16e specification corrigendum 1, 2 for mobile broadband access and WiMAX Forum system profile Wave2. The chipset is comprised of a 632.7-mW/24.99-mm2 modem/router chip and a 364-mW/11.05- mm2 dual-band 2 × 2 MIMO RF transceiver chip, both developed in 65-nm CMOS process. The proposed chipset is capable of handling a maximum peak WiMAX downlink (DL) throughput of 70 Mbps. Moreover, the chipset can reach up to -100.5-dBm sensitivity in a 10-MHz AWGN channel, which outperforms WiMAX Forum mobile radio conformance test (MRCT) by 9.5 dB. Such high sensitivity is due to the proposed low-noise high-linearity RF transceiver chip, which has 2.5-dB RX noise figure (NF) and -37-dB TX error vector magnitude (EVM), and the applied high-performance baseband signal processing algorithms. Several low-power design techniques-from SW level, firmware/DSP level, to HW module level-have been implemented to enable portable applications. The modem/router chip is highly integrated and has rich features and various interfaces for applications such as router or VoIP phone. Furthermore, this is the only published WiMAX chipset which has been in mass production.

A GSM/EDGE transmitter in 0.13-μm CMOS using offset phase locked loop and direct conversion architecture

A GSM/EDGE transmitter implemented in 0.13-mum CMOS using offset phase locked loop and direct conversion architecture is presented. The transmitter consists of a DCT, an OPLL with a TXVCO, a fractional-N synthesizer with a RFVCO and LDO regulators. The transmitter delivers 1.5 dBm output power with 1.2deg rms phase error and the modulation spectrum at 400 kHz offset is better than -62 dBc in high band GSM mode. In high band EDGE mode, it has maximum 4 dBm output power with 0.5 dB gain step per bit for 36 dB dynamic range and 2% rms error vector magnitude. The current consumption of high band is 171 mA at GSM mode and 169 mA at EDGE mode under proper output power level for PA. This chip is housed in a 56-pin QFN package.