George Chien

A 24.7dBm all-digital RF transmitter for multimode broadband applications in 40nm CMOS

Recently, digitizing RF circuits has attracted extensive attention by exploiting high speed transistors offered in nano-scale CMOS processes. The digitally-assisted or digital-intensive RF transceivers not only benefit from technology scaling in terms of power efficiency and die area, but also improve functional flexibility. The polar architecture is well recognized for digital RF transmitters [1,2,4,5], while the bandwidth expansion resulting from Cartesian-to-polar transformation makes it difficult to comply with high-speed wireless standards. Open-loop phase interpolation topology was employed in an outphasing transmitter [3], where 12dBm output power was demonstrated with 40MHz 802.11n signal. In this work, an all-digital RF transmitter with direct quadrature architecture is presented to address the need for broadband wireless connectivity.

A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC

A quad-band GSM/GPRS/EDGE receiver, implemented in 65 nm CMOS, complies with the ETSI standard without the need of external SAW filters. By exploring the properties of passive mixers and current-mode operation from RF to baseband, the receiver can achieve a SAW-filter-like selectivity with inexpensive on-chip components such as resistors and capacitors. In addition, to alleviate the linearity bottleneck at the LNA input stage, Class-AB self-bias LNTA is employed to break the conventional trade-offs among NF, linearity and power consumption. For single-to-differential conversion, external LC-CL baluns (instead of on-chip baluns) are used to balance the on-chip die and external BOM cost. This receiver solution is embedded as a part of a cellular phone SoC and achieves <; - HOdBm sensitivity, >; +1 dBm Out-of-Band Pι dB and consumes 58.9 mA. In FTA test, the receiver passes out-of-band blocker test with >; 4 dB margin.

A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC

Over the last decade, significant progress has been made towards increasing integration and reducing bill of material (BOM) for GSM/GPRS/EDGE cellular systems. In modern cellular phones, transmit SAW filters have been largely eliminated with innovative TX architecture and circuits [1] while receive SAW filters are still present. This remains as one of the few bottlenecks in achieving a true low-cost single-chip solution which offers a genuine advantage for high-volume applications. The main challenges of eliminating SAW-based bandpass filters from multiband 2G/2.5G receivers lie in noise-figure (NF) degradation and gain desensitization induced by 0dBm blockers at merely 20MHz away from the −99dBm in-band signal at GSM850/900 band. Furthermore, these unfiltered inter-ferers cause a strong reciprocal mixing effect and result in additional SNR degradation. Therefore, a SAW-less RX is required to have an extremely high dynamic range while maintaining best-in-class NF, LO wideband phase noise (PN) and spur performance.

A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS

In recent years, the increasing popularity of mobile devices, such as smart- phones and tablets, is driving the demand for integrating multiple radios on a single SoC to reduce cost, form factor and external BOM. These devices require ubiquitous wireless connectivity, which means concurrent operation with different radios. While concurrent operation of multiple radios brings excellent user experiences, there exist great challenges in dealing with radio co-existence in an SoC. For example, concurrent operation between WiFi and BT, both oper- ating in the 2.4GHz ISM band, sets additional requirements in RF front-end cir- cuits and system control. In addition, thermal effect of the integrated WiFi PA needs to be compensated to minimize its impact on the frequency-precise GPS system.

A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter

A novel highly-efficient multi-band multi-mode all-digital quadrature transmitter is presented. In the transmitter, a switching-mode power amplifier (PA), also referred to as digital power amplifier (DPA), which consists of an in-phase PA (I-PA) and a quadrature PA (Q-PA), is controlled by the digital codewords based on an input signal to turn on and off the power cells inside the I-PA or the Q-PA. Due to the load interaction between the I-PA and the Q-PA, a 2-dimensional (2-D) digital pre-distortion (DPD) is applied to linearize the DPA. The whole transmitter is implemented in 40 nm CMOS LP process and occupies a die area of 0.7 mm2. The all-digital quadrature transmitter can support 20 MHz, 40 MHz, and 80 MHz WiFi signals, Band 38 and Band 40 LTE signals with class 3 output power, and Bluetooth BDR, EDR2, and EDR3 signals.

A GPS/Galileo SoC with adaptive in-band blocker cancellation in 65nm CMOS

The proliferation of location-based applications inside various handheld electronic devices, such as mobile phones and internet tablets, demands the GPS system to have low power consumption, small form-factor and be co-located on the same device with other radio systems, such as cellular, BT, and WLAN. The conventional GPS solution often uses two SAW filters, before and after an external LNA, to meet the requirements of low noise and multi-radio coexistence. Nevertheless, it is highly desirable to remove the external LNA and interstage SAW filter due to size and cost, which presents a great design challenge to achieve high out-of-band linearity with very low power consumption. To fulfill these stringent requirements, a more comprehensive approach is needed to target a radio architecture with a proper RX system budgeting and optimal circuit design. In addition, a GPS system can be desensitized by unexpected in-band blockers generated from other subsystems on the same platform, such as LCD display, PMU, CPU system clocks, etc. The GPS digital baseband processor must possess the capability to withstand in-band blockers without significant performance degradation. This paper presents a GPS/Galileo SoC with an adaptive in-band blocker cancellation scheme, which is implemented in a 65nm CMOS process.

A 60nm WiFi/BT/GPS/FM combo connectivity SOC with integrated power amplifiers, virtual SP3T switch, and merged WiFi-BT transceiver

A highly integrated WiFi/BT/FM/GPS connectivity combo SOC is implemented in a 60nm CMOS process. This work presents the proposed WiFi/BT merged RF transceiver, a virtual SP3T switch, and DPD algorithm to save chip area, reduce BOM and enhance performance simultaneously. The WiFi/BT/FM/GPS RF transceiver areas are 1.7/1.3/0.8/1.0mm2, respectively. The measured WiFi 11g 54Mbps RX sensitivity is -78dBm and Pout is 20dBm with EVM of -28dB. The measured BT GMSK RX sensitivity is -94dBm and Pout is 10dBm. FM sensitivity is -110dBm and GPS cold/hot-start TTFF sensitivity is -148/-163dBm.

A 2×2 MIMO 802.11 abgn/ac WLAN SoC with integrated T/R switch and on-chip PA delivering VHT80 256QAM 17.5dBm in 55nm CMOS

This paper describes 2×2 MIMO 802.11ac Stage 1 WiFi + BT combo SoC chip with integrated dual-band PAs, LNAs, T/R switches, as well as a power management unit. The measured RX sensitivity of OFDM54M is -77.5dBm/ -77dBm in 2.4GHz and 5GHz, respectively. With the proposed broadband TX architecture, a high output power of 17.5dBm for 802.11ac Stage 1 VHT80 256QAM was achieved, and is extendable to the upcoming 802.11ac Stage2 VHT160. The maximum throughput achieved is 580Mbps in VHT80 MCS9 two-spatial stream mode, AWGN channel, with short GI. This chip occupies 27.8mm2 in 55nm 1P6M CMOS technology in which the MIMO WiFi RF and analog circuits occupies 7.7mm2.

A highly-efficient multi-band multi-mode digital quadrature transmitter with 2D pre-distortion

A novel highly-efficient multi-band multi-mode all digital quadrature transmitter is presented. The all digital transmitter uses in-phase (I) codeword and quadrature (Q) codeword to control a switching-mode power amplifier (PA) or digital PA (DPA) consisting of in-phase PA (I-PA) and quadrature PA (Q-PA), where each of the power cells inside I-PA or Q-PA is either on or off. Due to the load interaction between I-PA and Q-PA, a 2-dimensional digital pre-distortion is applied to linearize DPA. The total transmitter is implemented in 40nm CMOS LP process and occupies a die area of 0.7mm2. The digital quadrature transmitter can support 20MHz, 40MHz, and 80MHz WiFi signals, Band 38 and Band 40 LTE signals with class 3 output power, and Bluetooth BDR, EDR2, and EDR3 signals.

A dual-band 802.11abgn/ac transceiver with integrated PA and T/R switch in a digital noise controlled SoC

This paper describes a dual-band 802.11abgn/ac compliant transceiver in a 4-in-l combo connectivity SoC. It integrates the PAs, LNAs, T/R switches, and the 5GHz Balun. Due to the transmitter architecture and adaptive biasing scheme both are tailored for wide bandwidth, the 5GHz transmitter achieves 18.2dBm average output power for 802.11ac VHT80 MCS9 (Modulation and Coding Scheme 9). Within the 80MHz channel bandwidth, the IQ mismatch becomes frequency dependent, and is compensated through calibration. In the 2.4GHz transmitter, its PA load-line is adjustable. The power efficiency is thus remained similarly regardless the output power is at 20dBm for long range operation, or 8dBm for short range operation. By controlling the turn-on resistance of power island switch in digital baseband, and properly sizing the filler cap, the switching noise can be well controlled. The chip occupies 24.9mm2 in 55nm 1P6M CMOS technology, where 1.3mm2 is for 5GHz WLAN and 2.1mm2 is for 2.4GHz WLAN/BT.