Chia-Lung Ni

Nitrification–Denitrification of Opto-electronic Industrial Wastewater by Anoxic/Aerobic Process

Abstract This research focused on the biological treatment of high-strength organic nitrogen wastewater, and presented the results from the nitrification and denitrification of an actual industrial wastewater using anoxic/aerobic process. The opto-electronic industrial wastewater often contains a significant quantity of organic nitrogen compounds and has a ratio over 95% in organic nitrogen (Org-N) to total nitrogen (T-N). In this study, a 2-stage anoxic/aerobic process was established and evaluated the efficiency of wastewater treatment. Raw wastewater from an actual TFT-LCD manufacturing plant was obtained as the sample for looking into the feasibility of opto-electronic industrial wastewater treatment. After toxicity identification evaluation (TIE) test of raw wastewater, the inhibition was related to organic nitrogen (TMAH, MEA) and unionized ammonia (free ammonia, NH3) with high pH. Therefore, pH control is important for biological treatment of high-strength organic nitrogen industrial wastewater. Besides, hydraulic retention time (HRT) and mixed liquor recycled rate (MLR) were controlled independently to distinguish between the effects of these two factors. Under suitable HRT (>1.7 d) and mixed liquor recycled rate (<4Q), effluent of NH4-N, NO3-N + NO2-N, and COD can fall below 20 mg/L, 30 mg/L, and 80 mg/L. The anoxic/aerobic process removed 92–98% of the carbon source, and approximately 80% of TKN, 70% of T-N.

Boundary Conduction Mode Controlled Power Factor Corrector With Line Voltage Recovery and Total Harmonic Distortion Improvement Techniques

The proposed line voltage recovery (LVR) and the total harmonic distortion improvement (THDI) technique improve power factor (PF) and total harmonic distortion (THD) over a wide line voltage range in boundary conduction mode controlled power factor corrector (PFC). The LVR detects the input line root-mean-square voltage to generate the digital equivalent code to the THDI for optimizing the THD by tuning the on-time value at different line voltages. In addition, the LVR and the THDI provide a feedforward path to reduce the ripple of the feedback voltage for further improving the THD. Therefore, the PFC controller can keep high PF and low THD over a wide line voltage. Experimental results demonstrate that the peak PF value is 0.998 and the minimum THD is 1.7% by the test circuit fabricated in a TSMC 800-V ultrahigh-voltage process with the universal line voltage range of 90-264 V.

Perturbation On-Time (POT) Technique in Power Factor Correction (PFC) Controller for Low Total Harmonic Distortion and High Power Factor

The proposed perturbation on-time technique suppresses total harmonic distortion (THD) and, thus, improves the power factor in the power factor correction (PFC) controller. Besides, the adaptive control of the minimum off time by the proposed inhibit time control can improve efficiency even at low ac input voltage. Therefore, highly integrated PFC converter fabricated in the TSMC 800-V ultrahigh voltage process can achieve low THD of 6%, high PF of 99%, and high efficiency of 95% at the output power of 90 W.

Perturbation on-time (POT) control and inhibit time control (ITC) in suppression of THD of power factor correction (PFC) design

The paper presented the perturbation on-time (POT) control technique to suppress the total harmonic distortion (THD) to improve the performance of the power factor correction (PFC) in the AC-DC converter. Simultaneously, it can improve the efficiency through the proposed inhibit time control (ITC) mechanism at low AC input voltage. The test circuit fabricated in TSMC 800V UHV process can show the highly-integrated PFC controller. Experimental results demonstrate low THD of 8%, which results in high PF of 99%. Besides, high efficiency of 95% can be ensured at the output power of 90W.

Time-Shift Current Balance Technique in Four-Phase Voltage Regulator Module with 90% Efficiency for Cloud Computing

Four power stages for voltage regulator module (VRM) are adopted to provide high current driving capability and low output ripple in cloud computing. Thus, the time-shift current balance (TSCB) technique is proposed to achieve high performance power supply for servers. In addition, the power request, which includes the number of active phases and voltage identification, is acknowledged by servers for high driving capability during high throughput and high efficiency during standby mode. Furthermore, to equally distribute the current in each phase, the proposed TSCB technique in either voltage-mode or peak current-mode control improves the current balance performance and solves the stability problem. In the scale-down clouding computing prototype, the efficiency can be kept higher than 90% over a wide load current range of 2 A. In addition, the performance and operating frequency of the servers in stable operation are not limited by the VRM with the TSCB technique.

High-PF and ultra-low-THD power factor correction controller by sinusoidal-wave synthesis and optimized THD control

The proposed sinusoidal-wave synthesis (SWS) and the optimized THD control (OTC) improve power factor (PF) and total harmonic distortion (THD) over a wide line voltage range. The SWS detects the input line root-mean-square (rms) voltage to generate the digital equivalent code to the OTC for optimizing the THD by tuning the on-time value. Besides, the SWS and the OTC provide a feedforward path to reduce the ripple of the feedback voltage for further improving the THD. Therefore, the PFC converter can keep high PF and low THD over a wide line voltage. Experimental results demonstrate the PF is higher than 0.99 and the THD is 1.7% at VAC of 90-110V by the test circuit fabricated in TSMC 800V UHV process.

Thermoelectric energy harvesting with 1mV low input voltage and 390nA quiescent current for 99.6% maximum power point tracking

In this paper, the proposed voltage trend detection (VTD) circuit effectively achieves high tracking efficiency in mixed-signal maximum power point tracking (MPPT) for the thermoelectric energy harvesting. The input power ranges from 42nW to 1.67mW and the input voltage can be lower to 1mV with a low quiescent current of 390nA when circuit is designed to operate in weak-inversion region. Consequently, the exponential relationship of the characteristic in the weak-inversion region can ensure that the tracking efficiency is higher than 99.6% and the tracking response time is less than 34ms.

800V ultra-high-voltage start-up mechanism for pre-regulator in power factor correction (PFC) controller

The on-chip 800V ultra-high-voltage (UHV) start-up mechanism was introduced in this paper. Using the UHV start-up mechanism can minimize the current leakage at the AC input and remove the need of external start-up resistor and capacitor. As a result, the standby current can be decreased to improve the efficiency of AC-DC systems. Furthermore, the zero current detection (ZCD) circuit was used here to ensure the work of the pre-regulator. An inductance coil will detect the primary inductance current and reflect the voltage, which is detected by ZCD circuit to provide the energy to the pre-regulator. The test circuit fabricated in TSMC 800V UHV process can show the highly-integrated PFC controller. Experimental results demonstrate low THD of 8%, which results in high PF of 99%. Certainly, high efficiency of 95% can be ensured at the output power of 50W.

Triple loop modulation (TLM) for high reliability and efficiency in Power Factor Correction (PFC) system

Reliability of the Power Factor Correction (PFC) system was improved by fast transient response using the proposed triple loop modulation (TLM). Low bandwidth of less than 20 Hz that rejects AC source of 60/120 Hz coupling deteriorated system reliability in case of output load variation. The proposed TLM can automatically adjust bandwidth to rapidly increase or decrease inductor current in order to shorten transient response time. In steady state, system stability can be guaranteed by low-frequency compensation pole without being affected by TLM. The test circuit fabricated in VIS 500 V UHV LDMOS process demonstrated the performance of the highly-integrated PFC controller with the proposed TLM. Experimental results showed that the PFC system with TLM has high PF of 99%, high efficiency of 95%, and high power driving capability of about 90 W. The improvement in transient response is twofold faster than conventional PFC design with output load variation from 90W to 45 W and vice versa.

Variable sampling slope (VSS) and no-deadtime ramp generator (NDRG) techniques for closed-loop interleaving power factor correction (PFC) design with suppression of current mismatch

The proposed interleaving power factor correction (PFC) can effectively reduce the size of the AC-DC converter for portable electronics. Fully integrated variable sampling slope (VSS) technique can provide precise phase regulation under variable line voltage. Besides, the no-deadtime ramp generator (NDRG) records the previous status to modify the sequent on-time value to achieve current sharing for suppressing the total harmonic distortion (THD) and restraining the input current ripple, EMI filter, and the size of input inductor. Therefore, more power can be provided by the proposed interleaving PFC than that of single-phase PFC. Simultaneously, the drawback of the peak current twice than the average current in the Boundary control mode (BCM) can be greatly reduced. The test circuit fabricated in the TSMC 0.5μm 800V UHV process shows the highly integrated interleaving PFC can deliver high power of 180W with improved phase regulation precision.