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Dive into the research topics where Chia-Shih Cheng is active.

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Featured researches published by Chia-Shih Cheng.


Semiconductor Science and Technology | 2005

Power and linearity comparisons of gate- and source-terminated field-plate pseudomorphic HEMTs

Hsien-Chin Chiu; Chia-Shih Cheng; Yuan-Jui Shih

GaAs-based pseudomorphic high electron mobility transistors (pHEMTs) in which the field-plate (FP) is connected to the gate terminal and the source terminal, were developed and evaluated experimentally to determine their microwave and power performance. The small gate-to-drain feedback capacitance (Cgd) and the stable FP-induced depletion region at high input power (Pin) of the source-terminated FP pHEMT (FP-S pHEMT) greatly improve the power and linearity of the FP-S pHEMT above those of the gate-terminated FP pHEMT (FP-G pHEMT). The power ratio of the fundamental to the third-order inter-modulation product (IM3) is 18.8 dBc for FP-S pHEMT for Pin = 0 dBm; the corresponding value for FP-G pHEMT is 12.4 dBc. These experimental results indicate that the FP architecture is more effective at high-power operation and exhibits high linearity in high-power pHEMT applications.


IEEE Transactions on Electron Devices | 2011

Development of a New pHEMT-Based Electrostatic Discharge Protection Structure

Qiang Cui; Chia-Shih Cheng; Juin J. Liou; Hsien-Chin Chiu

Electrostatic discharge (ESD) protection structures in the GaAs technology are commonly constructed using enhancement-mode single-gate (SG) pseudomorphic high-electron mobility transistor (pHEMT) devices. This paper develops an improved ESD protection clamp based on a novel multigate pHEMT. With approximately the same layout area, the proposed ESD protection clamp can carry an ESD current three times higher than the conventional SG pHEMT clamp under the human body model stress. Moreover, the new ESD clamp shows promising results when characterized under the charged device model stress. The parasitic capacitance of the new ESD clamp is also measured to assess its suitability for high-frequency ESD applications.


Electrochemical and Solid State Letters | 2006

High Uniformity ( Al0.3Ga0.7 ) 0.5In0.5P ∕ InGaAs Enhancement-Mode Pseudomorphic HEMTs by Selective Succinic Acid Gate Recess

Hsien-Chin Chiu; Chia-Shih Cheng; Yuan-Jui Shih

High selectivity succinic acid: H 2 O 2 solution (SA) wet etching processes were used in the gate recess process to fabricate (Al 0 . 3 Ga 0 . 7 ) 0 . 5 In 0 . 5 P quaternary enhancement-mode pseudomorphic high electron mobility transistors (E-mode pHEMT). High uniformity of threshold voltage (V t h ) was achieved due to a high wet etching selectivity during gate recess process. In this study, we improved the power density and uniformity of the device by using wide bandgap (Al 0 . 3 Ga 0 . 7 ) 0 . 5 In 0 . 5 P Schottky layers. In addition, the best wet etching selectivity between GaAs and (Al 0 . 3 Ga 0 . 7 ) 0 . 5 In 0 . 5 P was obtained for large area power transistors. The developed 0.5 μm long and 1.2 mm wide gate FETs exhibited a V t h of +0.1 V and a maximum drain current (I d m a x ) of 385 mA/mm. The maximum output power at 1.9 GHz was 95 mW/mm with a linear power gain of 22 dB and a power-added efficiency of 60%. These characteristics demonstrate this novel E-mode pHEMTs have great potential for use in microwave power device applications.


Semiconductor Science and Technology | 2006

High uniformity enhancement- and depletion-mode InGaP/InGaAs pHEMTs using a selective succinic acid gate recess process

Hsien-Chin Chiu; Chia-Shih Cheng; Yuan-Jui Shih

High uniformity enhancement-mode (E-mode) and depletion-mode (D-mode) InGaP/InGaAs pseudomorphic high electron mobility transistors (pHEMTs) have been developed on 6 inch GaAs substrate using a selective succinic acid gate recess process. The 0.5 ?m long gate fingers of E-mode and D-mode pHEMTs are deposited simultaneously in this process simplification. The InGaP/InGaAs E-mode pHEMT exhibits a maximum drain-to-source current (Ids) of 460 mA mm?1, and a maximum transconductance (gm) of 430 mS mm?1. At 5.2 GHz operation, 216 mW mm?1 power density, 40% power-added efficiency and a 0.81 dB minimum noise figure (NFmin) are also achieved for the E-mode device. In this study, D-mode pHEMTs are applied for a switch monolithic microwave integrated circuit which provides an insertion loss of ?1.8 dB and isolation of ?9.2 dB under 28 dBm input power (Pin) and 5.5 GHz operation. From these measured results, this uniform E/D-mode InGaP/InGaAs pHEMT technology exhibits a high potential for WLAN applications.


Semiconductor Science and Technology | 2006

Microwave performance of AlGaAs/InGaAs pseudomorphic HEMTs with tuneable field-plate voltage

Hsien-Chin Chiu; Chia-Shih Cheng; Chien-Cheng Wei

GaAs-based pseudomorphic high electron mobility transistors (pHEMTs) in which the field-plate (FP) metal is supplied with various biases were developed and evaluated experimentally to determine their microwave and power performance. To minimize the strong electric field between drain and gate terminals, the field-plate technique in pHEMT fabrication was used in the past. In this study, the device breakdown voltage was found to reduce with the voltage of the field-plate metal (VFP). Owing to the depth modulation of the field-plate-induced depletion region at various field-plate biases, the device dc, RF, flicker noise and power performance were also influenced by tuneable VFP. This technique is easy to apply, based on standard pHEMT fabrication, and especially attractive for high-linearity power amplifiers by connecting VFP to negative bias.


IEEE Electron Device Letters | 2010

On-State and Off-State Breakdown Voltages in GaAs PHEMTs With Various Field-Plate and Gate-Recess Extension Structures

Hsien-Chin Chiu; Chia-Shih Cheng

GaAs pseudomorphic high-electron mobility transistors (PHEMTs) with various field-plate (FP) and gate-recess (GR) extensions were fabricated. Their on-state resistance (R on), breakdown voltage, flicker noise, and microwave characteristics were investigated. The FP length and GR width extensions can be controlled to improve significantly the breakdown voltage of PHEMTs. The design-of-experiment approach was employed with 16 transistors. The FP length extension was found to improve efficiently the off-state breakdown voltage (BV off) because of its suppression of the thermionic-field emission of gate electrons. However, an FP-induced depletion region cannot easily suppress channel impact ionization, which dominates the on-state breakdown voltage (BV on). Additionally, the FP length extension reduces the flicker noise of a device that is caused by surface states. The GR width extension has an opposite effect, because the exposed area of the uncap Schottky layer exposure increases with the GR width.


IEEE Electron Device Letters | 2008

Phase-Noise Improvement of GaAs pHEMT K-Band Voltage-Controlled Oscillator Using Tunable Field-Plate Voltage Technology

Hsien-Chin Chiu; Chien-Cheng Wei; Chia-Shih Cheng; Yu-Fei Wu

This letter presents a voltage-controlled oscillator (VCO) with low phase-noise performance by applying tunable field-plate (FP) voltage on 0.15-mum-gate-length GaAs pseudomorphic high-electron-mobility transistors (pHEMTs). In this letter, the FP metal between gate and drain terminals was connected to a single pad and was controlled by an extra voltage supplier (VFP). Owing to the depth modulation of FP-induced depletion region at various FP voltages, the device flicker noise was also improved by applying negative VFP. This technique is convenient to be applied in standard pHEMT fabrication and particularly attractive for reducing the phase noise of VCO design without extra power consumption. A tunable phase-noise inductor-capacitor feedback 21-GHz VCO was demonstrated. The measured phase noise of this novel design is -95 dBc/Hz at an offset frequency of 1 MHz, and this value can be improved to -99.6 dBc/Hz at VFP of -5.5 V. The core dc-power consumption of this circuit is 30.8 mW.


IEEE Transactions on Electron Devices | 2009

A High-Linearity Single-Pole-Double-Throw Pseudomorphic HEMT Switch Based on Tunable Field-Plate Voltage Technology

Hsien-Chin Chiu; Chia-Shih Cheng; Shao-Wei Lin; Chien-Cheng Wei

A high-isolation high-linearity GaAs pseudomorphic high-electron mobility transistor single-pole-double-throw microwave switch was developed using a tunable field-plate (FP) bias voltage technology. In this paper, a piece of FP metal was deposited between 0.15-mum-long gate and drain terminals. An extra FP-induced depletion region was generated to suppress the harmonics of switching associated with OFF-state operation. When switching into the ON-state, the FP switch is associated with an insertion loss similar to that of the standard switch below 6 GHz. However, the isolation performance can be enhanced by 10 dB using an FP technology, which reduces the OFF-state capacitance that is produced by the extra FP-induced depletion region. The FP provides an additional mechanism to suppress the power of the second- and third-order harmonics in the OFF-state with slight ON-state insertion-loss degradation.


Semiconductor Science and Technology | 2008

Comprehensive study of gate-terminated and source-terminated field-plate 0.13 µm NMOS transistors

Hsien-Chin Chiu; Shao-Wei Lin; Chia-Shih Cheng; Chien-Cheng Wei

This study systematically investigated microwave noise, power and linearity characteristics of field-plate (FP) 0.13 µm CMOS transistors in which the field-plate metal is connected to the gate terminal and the source terminal. The gate-terminated FP NMOS (FP-G NMOS) provided the best noise figure (NF) at 6 GHz compared with standard devices and the source-terminated FP device (FP-S NMOS) as the lowest gate resistance (Rg) was obtained by this structure. By adopting the field-plate metal in NMOS, both FP-S and FP-G devices achieved higher current density at high gate bias voltages. Moreover, these two devices also had higher efficiency under high drain-to-source voltages at the high input power swing. The third-order inter-modulation product (IM3) is −39.4 dBm for FP-S NMOS at Pin of −20 dBm; the corresponding values for FP-G and standard devices are −34.9 dBm and −37.3 dBm, respectively. Experimental results indicate that the FP-G architecture is suitable for low noise applications and FP-S is suitable for high power and high linearity operation.


asia-pacific microwave conference | 2007

A Compact Size Ka Band pHEMT MMIC Frequency Tripler with CPW Technology

Shao Wei Lin; Chia-Shih Cheng; Chien-Cheng Wei; Hsien-Chin Chiu; Rong-Jyi Yang

This paper presents an novel configuration of balanced frequency InGaAs pseudomorphic high electron mobility transistor (PHEMT) monolithic microwave integrated circuit (MMIC) tripler with Ka-band output frequency (39 GHz). A resonant LC filter is used to eliminate the fundamental frequency and a phase delay line is employed to suppress the second harmonic. By using a class B transistor bias point and carefully selecting its input and output terminations, a conversion loss of 16.36 dB for an 10 dBm input signal have been obtained. As compared to the third-harmonic frequency, the second harmonic is more than 28.1 dB at 39 GHz. It is very useful for applications in the wireless communication and radar systems.

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Yu-Fei Wu

Chang Gung University

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