Chien-Cheng Wei

An ultra-wideband CMOS VCO with 3-5 GHz tuning range

An ultra-wideband CMOS voltage-controlled oscillator (VCO) with 3-5 GHz tuning range is presented in this paper. The circuit was designed and fabricated by using TSMC 0.18-/spl mu/m CMOS process. The proposed VCO is using the tunable active inductor to replace the passive spiral inductor. The active inductor can vary the inductance between 1.5/spl sim/7 nH with quality-factor > 30 by a feedback tunable resistor. Comparisons of this topology with conventional VCO show that this topology achieves better performance with very wide tuning range and compact chip size. The tuning range is approximately from 3 to 5 GHz for ultra-wideband system applications.

A novel compact complementary Colpitts differential CMOS VCO with low phase-noise performance

A low phase-noise Ka-band CMOS voltage-controlled oscillator is proposed in this paper. The CMOS VCO core adopts a new complementary Colpitts structure in a 0.18- mum CMOS technology to achieve the differential-ended outputs with low phase-noise performance, as well as operate at much higher frequency. The VCO oscillates from 29.8 to 30 GHz with 200 MHz tuning range. The measured phase-noise at 1-MHz offset is -109 dBc/Hz at 30 GHz and 105.5 dBc/Hz at 29.8 GHz. The power consumption of the VCO core is only 27 mW. To the authorspsila knowledge, the proposed CMOS VCO achieves the best figure of merit (FOM) of -185 dB at 29.95- GHz band.

A 12-GHz Low-Phase-Noise Voltage-Controlled Oscillator Using Novel Field-Plate CMOS Transistors

This paper presents a voltage-controlled oscillator (VCO) with low-phase-noise performance based on 0.13-mum field- plate (FP) CMOS transistors. The proposed FP transistors exhibit lesser flicker noise (1// noise) than the standard transistors because electron flow is suppressed in the deeper channel. Cross-coupled 12-GHz VCO with standard and FP transistors was simultaneously designed and fabricated in a TSMC 0.13-mum CMOS process. The measured phase noise of this novel design is -122 dBc/Hz at an offset frequency of 1 MHz. This novel design offered an average 5-dBc phase-noise improvement over the VCO with standard transistors at offset frequencies from 100 kHz to 1MHz.

A 24GHz low-power CMOS receiver design

A 24 GHz low-power CMOS RF receivers for indoor wireless application is developed in this paper. This paper presents a novel approach to integrate the RF front-end circuits, and realizes the manufacture of SoC (System on a Chip) design. The proposed RF IC includes a low-noise amplifier (LNA), a down-conversion mixer, a voltage-controlled oscillator (VCO) and a variable gain amplifier (VGA). For the demands of a low- power design, the LNA and VCO were designed with current- reused technology for lowering the dc power consumption, and the current-bleeding approach was adopted in mixer design for boosting its conversion gain, respectively. The proposed 24 GHz CMOS RF receiver achieves the overall conversion gain of 23.4 dB with noise figure of 5.4 dB, and the total power consumption is only 31.65 mW. Compared to the other papers published over the past few years, this paper exhibits a better potential in low-power design than other receivers applied in the same frequency band.

High-Linearity Performance of 0.13-

This letter presents high-linearity 0.13-mum CMOS devices based on field-plate technology. The field-plate technology reduces the electric field between the gate and drain terminals, subsequently forming a field-plate-induced depletion region and reducing the leakage current to significantly improve linearity and power of the CMOS devices. The third-order intermodulation product of 0.13-mum NMOS devices with and without field-plate technology are -41.8 and -32.4 dBm, respectively, for input power of -10 dBm. Experimental results indicate that the field-plate architecture exhibits high linearity and power for CMOS RFIC applications

muhboxm

GaAs-based pseudomorphic high electron mobility transistors (pHEMTs) in which the field-plate (FP) metal is supplied with various biases were developed and evaluated experimentally to determine their microwave and power performance. To minimize the strong electric field between drain and gate terminals, the field-plate technique in pHEMT fabrication was used in the past. In this study, the device breakdown voltage was found to reduce with the voltage of the field-plate metal (VFP). Owing to the depth modulation of the field-plate-induced depletion region at various field-plate biases, the device dc, RF, flicker noise and power performance were also influenced by tuneable VFP. This technique is easy to apply, based on standard pHEMT fabrication, and especially attractive for high-linearity power amplifiers by connecting VFP to negative bias.

CMOS Devices Using Field-Plate Technology

This letter presents a voltage-controlled oscillator (VCO) with low phase-noise performance by applying tunable field-plate (FP) voltage on 0.15-mum-gate-length GaAs pseudomorphic high-electron-mobility transistors (pHEMTs). In this letter, the FP metal between gate and drain terminals was connected to a single pad and was controlled by an extra voltage supplier (VFP). Owing to the depth modulation of FP-induced depletion region at various FP voltages, the device flicker noise was also improved by applying negative VFP. This technique is convenient to be applied in standard pHEMT fabrication and particularly attractive for reducing the phase noise of VCO design without extra power consumption. A tunable phase-noise inductor-capacitor feedback 21-GHz VCO was demonstrated. The measured phase noise of this novel design is -95 dBc/Hz at an offset frequency of 1 MHz, and this value can be improved to -99.6 dBc/Hz at VFP of -5.5 V. The core dc-power consumption of this circuit is 30.8 mW.

Microwave performance of AlGaAs/InGaAs pseudomorphic HEMTs with tuneable field-plate voltage

In the near decade, following the advances in CMOS technology, RF CMOS circuits have been extensively applied in consumer products and wireless communication systems. Meanwhile, the demand of green design mechanism is becoming more and more important for circuit designs. This paper proposes the green design strategies for RF circuits, such as PA, LNA, mixer, and VCO. The design strategies focus on not only the low power consumption with reused bias current but also the small chip area for low spurious environment contamination. For the low-power design, some published literatures have been adopted the operation voltage from 3V down to only 0.2V, to save the dissipated dc power from tens mW to several hundreds of µW. Additionally, many design strategies and green figures of merit (GFOM) are also presented and proposed in this paper, for the future green RF circuit design.

Phase-Noise Improvement of GaAs pHEMT K-Band Voltage-Controlled Oscillator Using Tunable Field-Plate Voltage Technology

A high-isolation high-linearity GaAs pseudomorphic high-electron mobility transistor single-pole-double-throw microwave switch was developed using a tunable field-plate (FP) bias voltage technology. In this paper, a piece of FP metal was deposited between 0.15-mum-long gate and drain terminals. An extra FP-induced depletion region was generated to suppress the harmonics of switching associated with OFF-state operation. When switching into the ON-state, the FP switch is associated with an insertion loss similar to that of the standard switch below 6 GHz. However, the isolation performance can be enhanced by 10 dB using an FP technology, which reduces the OFF-state capacitance that is produced by the extra FP-induced depletion region. The FP provides an additional mechanism to suppress the power of the second- and third-order harmonics in the OFF-state with slight ON-state insertion-loss degradation.

Green design techniques for RF front-end circuits

This study systematically investigated microwave noise, power and linearity characteristics of field-plate (FP) 0.13 µm CMOS transistors in which the field-plate metal is connected to the gate terminal and the source terminal. The gate-terminated FP NMOS (FP-G NMOS) provided the best noise figure (NF) at 6 GHz compared with standard devices and the source-terminated FP device (FP-S NMOS) as the lowest gate resistance (Rg) was obtained by this structure. By adopting the field-plate metal in NMOS, both FP-S and FP-G devices achieved higher current density at high gate bias voltages. Moreover, these two devices also had higher efficiency under high drain-to-source voltages at the high input power swing. The third-order inter-modulation product (IM3) is −39.4 dBm for FP-S NMOS at Pin of −20 dBm; the corresponding values for FP-G and standard devices are −34.9 dBm and −37.3 dBm, respectively. Experimental results indicate that the FP-G architecture is suitable for low noise applications and FP-S is suitable for high power and high linearity operation.