Chia-Yun Cheng

18.6 A 0.5nJ/pixel 4K H.265/HEVC codec LSI for multi-format smartphone applications

A 4K×2K H.265/HEVC video codec chip is fabricated in a 28nm CMOS process with a core area of 2.16mm2. This LSI chip integrates a dual-standard (H.265 and H.264) video codec and a series of prevalent (VC-1, WMV-7/8/9, VP-6/8, AVS, RM-8/9/10, MPEG-2/4) decoders into a single chip. It contains 3,558K logic gates and 308KB of internal SRAM. Moreover, it simplifies intra/inter-rate-distortion optimization (RDO) processes and reduces external bandwidth via line-store SRAM pool (LSSP) and data-bus translation (DBT) techniques. For smartphone applications, it completes real-time HEVC encoding and decoding with 4096×2160 resolution and 30fps, and consumes 126.73mW (0.5nJ/pixel) of core power dissipation at 0.9V, at 494MHz (encoding) and 350MHz (decoding). 1080HD and 720HD resolutions are reported as well. The chip features are summarized in Fig. 18.6.1.

A full-HD 60fps AVS/H.264/VC-1/MPEG-2 video decoder for digital home applications

In this paper, an AVS-embedded multi-format video decoder is presented. It integrates AVS JP@L6.2, H.264 HP@L4.2, VC-1 AP@L3, and MPEG-2 MP@HL in a single chip and features resources sharing, memory management, and early-stage acqusition to facilitate cost and bandwidth efficiency. For the applications of broadcasting, an adaptive error concealment method is proposed. A chip is fabricated and integrates 415K logic gates and 682Kbits embeded SRAM in 65nm single-poly seven-metal CMOS process with area of 2.47mm2. AVS video decoding of full 1920×1088 high-definition sequences at 60 frames per second is achieved at 166MHz clock frequency with power dissipation of 41.3mW at 1.0V supply voltage.

A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications

A 4 K × 2 K H.265/HEVC video codec chip supporting 14 video standard formats is implemented on a 1.49 × 1.45 mm 2 die in a 28 nm CMOS process. Several HEVC fast algorithms reduce the coding modes by analyzing the content features leading to over 68.5% and 83% of complexity reduction in intra and inter coding, respectively. A fully parallel processing element (PE) array is adopted in SAO and IP/ME, which reduce number of accesses to SRAM by 48.7% and 78.4%, respectively. A shared memory management unit (MMU) including line-store SRAM pool (LSSP) and data bus translation (DBT) techniques efficiently reuses and packs the neighboring pixels which contribute 71.6% of external bandwidth reduction. This chip achieves 4096 × 2160@30 fps HEVC encoding/decoding and consumes 126.73 mW, 0.5 nJ/pixel of energy efficiency, under 494 MHz and 350 MHz of clock frequency, enabling 4 K video services for smart-phone applications.

A multi-format Blu-ray player SoC in 90nm CMOS

A Blu-ray Disc (BD) player, back-end SoC supporting multiple protection, video and display formats is fabricated in a 90nm 1P7M CMOS process with a core area of 62.95mm2. This SoC adopts a general copy protection (GCP) unit to integrate various kinds of protection algorithms (e.g. AES, CSS, CPPM/CPRM, DES, SHA-1/MD5), designs a dedicated memory management unit (MMU) for realizing multiple video standards (e.g. MPEG-1/2/4, H.264, VC-1), and exploits a reduced display path so as to provide two display outputs simultaneously. Moreover, a 3.7Gb/s/ch HDMI TX circuit is proposed to support different color depths and display resolutions. For BD player applications, AACS decryption, 60fps H.264 decode, 1080pHD with 480pSD picture overlay (PIP), and HDMI-1.3 12b deep color-mode output is achieved at 200MHz, 200MHz, 148.5MHz and 222.5MHz clock frequency, respectively. It dissipates about 1.605W at 1.0V core and 1.2/3.3V HDMI macro. The chip features are summarized in Fig. 8.4.1.

A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications

A first-reported 4K×2K@60fps and Main-10 HEVC video decoder integrating 14 video formats is fabricated in a 28nm CMOS process. It adopts an Adaptive Coding Unit Balance (ACUB) and Data-Sharing Wave-front Dual-core (DSWD) architectures to lower the required working frequency by 65%. A 10-bit Smart Pixel Storage (SPS) scheme is proposed to reduce the frame buffer space by 37.5%. Moreover, a weighted memory management unit (W-MMU) and multi-standard architecture reduce DRAM bandwidth and cost by 43% and 28%, respectively. This 4K Main-10 HEVC video decoder chip integrates 3.4M gate counts with area of 2.86mm2. It achieves 530Mpixels/s throughput which is two times larger than the state-of-the-art HEVC design [6] and consumes 0.2nJ/pixel energy efficiency, enabling real-time 4K video playback for UHD-TV applications.

Energy and area efficient hardware implementation of 4K Main-10 HEVC decoder in Ultra-HD Blu-ray player and TV systems

A 4K and Main-10 HEVC video decoder LSI is fabricated in a 28nm CMOS process. It adopts a block-concealed processor (BcP) to improve the visual quality and a bandwidth-suppressed processor (BsP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. It features fully core scalable (FCS) architecture which lowers the required working frequency by 65%. A 10-bit compact scheme is proposed to reduce the frame buffer space by 37.5%. Moreover, a multi-standard architecture reduces are by 28%. It achieves 530Mpixels/s throughput which is two times larger than the state-of-the-art HEVC design [2] and consumes 0.2nJ/pixel energy efficiency, enabling real-time 4K video playback in Ultra-HD Blu-ray player and TV systems.

A 2.6mm 2 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications

A lower power and area efficient VP9 and multi-standard video decoder chip is first-reported for Android 4K TV. It supports prevalent MPEG-x, VP-x, RMx, WMV-x and H.26x series video standards in a single chip. Three high-throughput techniques, look-ahead re-mapping, early stage pipeline and dynamic-scheduled bus translation, are proposed. They cuts the processing times by 51.2% compared to the state-of-the-art design [4]. Moreover, two area-efficient techniques, hybrid backward probability update and tile-to-raster scan ordering, are designed to reduce the internal memory size by 10%. A mass-production chip is fabricated in a 28nm CMOS technology with an energy efficiency of 0.19nJ/pixel and an area of 2.6mm2. Compared to the dual-core decoder design [4], this work achieves the identical performance (4K@60fps) with single core which cut one-half of chip area.

A 4K×2K@60fps multi-standard TV SoC processor with integrated HDMI/MHL receiver

A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory management unit and resource sharing technique to improve the throughput and area efficiency by 38.5% and 34.3%, respectively. Moreover, a lossless compression processor (LCP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. The proposed TV SoC processor includes multi-standard 4K×2K@60fps playback and 3.4Gbps HDMI receiver (Rx), and both scenario dissipate 198.15mW at 1.2V core and 3.3V I/O.

A 363-µW/fps power-aware green multimedia processor for mobile applications

In this paper, a power-aware and low power multimedia processor is presented. A novel clock gating scheme and dynamic frequency selection (DFS) are implemented to minimize the power dissipation and it integrates 7-standards (H.264 / VC1 / RV / AVS / MPEG-1 / MPEG-2 / MPEG-4) with several resource-sharing techniques in both algorithmic and architectural levels so as to achieve significant area and power reduction. In this work, our proposal also adopts several fine-grain power scalability (FGPS) technologies which can reduce a noticeable power consumption. The processor supports a wide range of decoding resolution ranging from CIF to full-HD under the 20~288MHz of working frequency and 60fps of frame rate with 363 μW/fps of power dissipation at 1.2V supply voltage and fabricated using 40nm 1P7M CMOS process with core area 1.40 mm2.

A 775-µW/fps/view H.264/MVC decoder chip compliant with 3D Blu-ray specifications

A first-reported, sub-mW/fps/view multi-view video decoder chip fully compliant to 3D Blu-ray specifications is reported. It explores the resource sharing so as to integrate not only single-view MPEG-2/VC-1/AVC but multi-view MVC standards into a single die. Moreover, it features pipeline management and clock management units so as to improve the processing throughput and clock power efficiency. A test chip for not only single-view video but multi-view H.264/MVC decoding has been designed and fabricated using 40nm 1P7M CMOS process with core area 1.22mm2. Core power dissipation is about 46.5mW under 1920×1080 resolution of single view 60fps or stereo-view 30fps.