Chi-cheng Ju

A 125Mpixels/sec full-HD MPEG-2/H.264/VC-1 video decoder for Blu-ray applications

A fully-compliant high-definition video decoder LSI for Blu-ray Disc (BD) player is presented. It supports MPEC-2 MP@HL, H.264 HP@L4.1, and VC-1 AP@L3 video decoding in a single chip and features resource sharing and memory management unit to achieve area/throughput efficiency. A test chip is fabricated and integrates 515 K logic gates with 522 Kbits of embedded SRAM in 90nm single-poly seven-metal CMOS process with area of 5.06 mm2. For Blu-ray player requirements, video decoding of full 1920times1080 high-definition sequences at 60 frames per second requires 125 Mpixels/sec of processing throughput which is two times higher than comparable designs [5][6] and is achieved at 200 MHz clock frequency with power dissipation of 317 mW at 1.0 V supply voltage.

18.6 A 0.5nJ/pixel 4K H.265/HEVC codec LSI for multi-format smartphone applications

A 4K×2K H.265/HEVC video codec chip is fabricated in a 28nm CMOS process with a core area of 2.16mm2. This LSI chip integrates a dual-standard (H.265 and H.264) video codec and a series of prevalent (VC-1, WMV-7/8/9, VP-6/8, AVS, RM-8/9/10, MPEG-2/4) decoders into a single chip. It contains 3,558K logic gates and 308KB of internal SRAM. Moreover, it simplifies intra/inter-rate-distortion optimization (RDO) processes and reduces external bandwidth via line-store SRAM pool (LSSP) and data-bus translation (DBT) techniques. For smartphone applications, it completes real-time HEVC encoding and decoding with 4096×2160 resolution and 30fps, and consumes 126.73mW (0.5nJ/pixel) of core power dissipation at 0.9V, at 494MHz (encoding) and 350MHz (decoding). 1080HD and 720HD resolutions are reported as well. The chip features are summarized in Fig. 18.6.1.

A full-HD 60fps AVS/H.264/VC-1/MPEG-2 video decoder for digital home applications

In this paper, an AVS-embedded multi-format video decoder is presented. It integrates AVS JP@L6.2, H.264 HP@L4.2, VC-1 AP@L3, and MPEG-2 MP@HL in a single chip and features resources sharing, memory management, and early-stage acqusition to facilitate cost and bandwidth efficiency. For the applications of broadcasting, an adaptive error concealment method is proposed. A chip is fabricated and integrates 415K logic gates and 682Kbits embeded SRAM in 65nm single-poly seven-metal CMOS process with area of 2.47mm2. AVS video decoding of full 1920×1088 high-definition sequences at 60 frames per second is achieved at 166MHz clock frequency with power dissipation of 41.3mW at 1.0V supply voltage.

A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications

A 4 K × 2 K H.265/HEVC video codec chip supporting 14 video standard formats is implemented on a 1.49 × 1.45 mm 2 die in a 28 nm CMOS process. Several HEVC fast algorithms reduce the coding modes by analyzing the content features leading to over 68.5% and 83% of complexity reduction in intra and inter coding, respectively. A fully parallel processing element (PE) array is adopted in SAO and IP/ME, which reduce number of accesses to SRAM by 48.7% and 78.4%, respectively. A shared memory management unit (MMU) including line-store SRAM pool (LSSP) and data bus translation (DBT) techniques efficiently reuses and packs the neighboring pixels which contribute 71.6% of external bandwidth reduction. This chip achieves 4096 × 2160@30 fps HEVC encoding/decoding and consumes 126.73 mW, 0.5 nJ/pixel of energy efficiency, under 494 MHz and 350 MHz of clock frequency, enabling 4 K video services for smart-phone applications.

A multi-format Blu-ray player SoC in 90nm CMOS

A Blu-ray Disc (BD) player, back-end SoC supporting multiple protection, video and display formats is fabricated in a 90nm 1P7M CMOS process with a core area of 62.95mm2. This SoC adopts a general copy protection (GCP) unit to integrate various kinds of protection algorithms (e.g. AES, CSS, CPPM/CPRM, DES, SHA-1/MD5), designs a dedicated memory management unit (MMU) for realizing multiple video standards (e.g. MPEG-1/2/4, H.264, VC-1), and exploits a reduced display path so as to provide two display outputs simultaneously. Moreover, a 3.7Gb/s/ch HDMI TX circuit is proposed to support different color depths and display resolutions. For BD player applications, AACS decryption, 60fps H.264 decode, 1080pHD with 480pSD picture overlay (PIP), and HDMI-1.3 12b deep color-mode output is achieved at 200MHz, 200MHz, 148.5MHz and 222.5MHz clock frequency, respectively. It dissipates about 1.605W at 1.0V core and 1.2/3.3V HDMI macro. The chip features are summarized in Fig. 8.4.1.

A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications

A first-reported 4K×2K@60fps and Main-10 HEVC video decoder integrating 14 video formats is fabricated in a 28nm CMOS process. It adopts an Adaptive Coding Unit Balance (ACUB) and Data-Sharing Wave-front Dual-core (DSWD) architectures to lower the required working frequency by 65%. A 10-bit Smart Pixel Storage (SPS) scheme is proposed to reduce the frame buffer space by 37.5%. Moreover, a weighted memory management unit (W-MMU) and multi-standard architecture reduce DRAM bandwidth and cost by 43% and 28%, respectively. This 4K Main-10 HEVC video decoder chip integrates 3.4M gate counts with area of 2.86mm2. It achieves 530Mpixels/s throughput which is two times larger than the state-of-the-art HEVC design [6] and consumes 0.2nJ/pixel energy efficiency, enabling real-time 4K video playback for UHD-TV applications.

Energy and area efficient hardware implementation of 4K Main-10 HEVC decoder in Ultra-HD Blu-ray player and TV systems

A 4K and Main-10 HEVC video decoder LSI is fabricated in a 28nm CMOS process. It adopts a block-concealed processor (BcP) to improve the visual quality and a bandwidth-suppressed processor (BsP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. It features fully core scalable (FCS) architecture which lowers the required working frequency by 65%. A 10-bit compact scheme is proposed to reduce the frame buffer space by 37.5%. Moreover, a multi-standard architecture reduces are by 28%. It achieves 530Mpixels/s throughput which is two times larger than the state-of-the-art HEVC design [2] and consumes 0.2nJ/pixel energy efficiency, enabling real-time 4K video playback in Ultra-HD Blu-ray player and TV systems.

A 360-degree 4K×2K panoramic video recording over smart-phones

A 4K×2K video processor supporting 360-degree video recording over the smart-phone is first-reported. Two 180° fisheye cameras are exploited to stitch the circle video into a panorama one. Fast stitching algorithms reused the neighboring pixel and reduce the unused operating area while keep high stitching quality, and therefore achieve 4K real-time recording over 2.5GHz octa-core ARM CPU and Power VR GPU.

Adaptive region of interest processing for panoramic system

An adaptive region-of-interest panoramic system is firstly proposed to achieve high-quality and real-time processing for 360-degree panorama. This technique prevents from processing a whole 360-degree image by only focusing on the particular area. Several memory optimizing methods, including cache-miss rate and memory buffer size reduction, are also applied with the purpose of improving the run time performance especially over the mobile devices. Experimental results show that the proposed system can offer 20 frames per second for 4K×2K 360-degree panorama over 2.2GHz Octa-core ARM CPU.

A 360-degree 4K×2K pan oramic video processing Over Smart-phones

A 4K×2K video processor supporting 360-degree processing over the smart-phone is first-reported. Two 182° fisheye cameras are exploited to warp and blend the circle video into a 4K panorama one. Fast blending architecture reused the memory buffer and reduce the unused operating area while keep high blending quality, and therefore achieve 4K 360-degree, equivalently 1K 90-degree video processing over 2.5GHz octa-core ARM CPU and Power VR GPU. From the experiment, he proposal achieves 1024×512@15fps which is 3.9 times higher than the state-of-the-art design [6].