Chiaki Dono

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

Two circuit techniques of DDR1/DDR2 compatible chip architecture designed for both high-speed and high-density DRAMs are presented. The dual clock input latch scheme, which reduces the excessive timing margin for random input commands by using a pair of latch circuits controlled by dual-phase 1-shot clock signals, achieves a 0.9-ns reduction in cycle time from 3.05 ns to 2.15 ns. By using these techniques in combination with a hybrid multi-oxide output buffer, we developed a 175.3 mm/sup 2/ 1Gb SDRAM which operates as a 800-Mb/s/pin DDR2 or 400Mb/s/pin DDR1.

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual clock input latch scheme and hybrid multi-oxide output buffer

This paper describes three circuit techniques for a DDR1/DDR2-compatible chip architecture designed for both high-speed and high-density DRAMs: 1) a dual-clock input-latch scheme, which reduces the excessive timing margin for random input commands by using a pair of latch circuits controlled by dual-phase one-shot clock signals, achieves a 0.9-ns reduction in cycle time from 3.05 to 2.15 ns; 2) a hybrid multi-oxide output buffer reduces the area penalty of the output buffer caused by compatible chip design from 1.35% to 0.3%; and 3) a quasi-shielded distributed data transfer scheme enables a 2.6-ns reduction in access time to 10.25 ns in both 2-b and 4-b prefetch operations. By using these techniques, we developed a 175.3-mm/sup 2/ 1-Gb SDRAM that operates as an 800-Mb/s/pin DDR2 or 400-Mb/s/pin DDR1.