Seiji Narui

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

We developed a 1-Gb/s/pin 512-Mb DDRII SDRAM composed of a digital delay-locked loop (DLL) and a slew-rate controlled output buffer. The digital DLL has a frequency divider for the DLL input, which performs at a operating frequency of up to 500 MHz at 1.6 V, and it provides internal clocking with 50% duty-cycle correction. The DLL has a current-mirror-type interpolator, which enables a resolution as high as 14 ps, is standby-current-free, and can operate at voltages as low as 0.8 V. The slew-rate impedance-controlled output buffer circuit reduces the output skew from 107 to 10 ps. This SDRAM was tested using a 0.13-/spl mu/m 126.5 mm/sup 2/ 512 Mb device.

A multi-gigabit DRAM technology with 6F/sup 2/ open-bit-line cell distributed over-driven sensing and stacked-flash fuse

To cope with difficult device miniaturization in the multi-gigabit era, memory cells smaller than the traditional 8F/sup 2/ folded bitline (BL) cell are needed. A 6F/sup 2/ trench capacitor folded-BL cell has been recently described. However, it needs not only additional tight-pitch layers to create a vertically folded-BL arrangement, but also a vertical transistor. The 6F/sup 2/ open-BL cell enabling a simple planar transistor is another candidate as its inherently large imbalance noise between pairs of BLs is reduced. Low-voltage, high-speed array operation is essential in the multi-gigabit era. A conventional non-over-driven sensing scheme cannot achieve a high enough speed at an array voltage below 1.6 V, because the threshold voltage (Vth) cannot be reduced <0.1 V to obtain a low enough stand-by current. Distributed over-driven sensing enables a higher speed due to reduced voltage loss caused by distributed drivers combined with meshed power lines. Consequently, compared with the conventional schemes, the sensing time for a 1.2 V array voltage necessary for the 1 Gb generation decreased by 6.9 ns and 2.0 ns. Hence, this sensing scheme is promising for array voltages below 1.0 V in multi-gigabit memory. In multi-gigabit DRAMs, redundancy for degraded cells after packaging is a major concern. To overcome this a scheme is adopted which features a stacked flash fuse composed of three series flash fuses utilizing standard CMOS transistors without any additional process steps. Thus this technology can be used to fabricate a 0.13 μm 180 mm/sup 2/ 1 Gb DRAM assembled in a 400-mil package.

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

Two circuit techniques of DDR1/DDR2 compatible chip architecture designed for both high-speed and high-density DRAMs are presented. The dual clock input latch scheme, which reduces the excessive timing margin for random input commands by using a pair of latch circuits controlled by dual-phase 1-shot clock signals, achieves a 0.9-ns reduction in cycle time from 3.05 ns to 2.15 ns. By using these techniques in combination with a hybrid multi-oxide output buffer, we developed a 175.3 mm/sup 2/ 1Gb SDRAM which operates as a 800-Mb/s/pin DDR2 or 400Mb/s/pin DDR1.

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual clock input latch scheme and hybrid multi-oxide output buffer

This paper describes three circuit techniques for a DDR1/DDR2-compatible chip architecture designed for both high-speed and high-density DRAMs: 1) a dual-clock input-latch scheme, which reduces the excessive timing margin for random input commands by using a pair of latch circuits controlled by dual-phase one-shot clock signals, achieves a 0.9-ns reduction in cycle time from 3.05 to 2.15 ns; 2) a hybrid multi-oxide output buffer reduces the area penalty of the output buffer caused by compatible chip design from 1.35% to 0.3%; and 3) a quasi-shielded distributed data transfer scheme enables a 2.6-ns reduction in access time to 10.25 ns in both 2-b and 4-b prefetch operations. By using these techniques, we developed a 175.3-mm/sup 2/ 1-Gb SDRAM that operates as an 800-Mb/s/pin DDR2 or 400-Mb/s/pin DDR1.

TCAD diagnosis of I/O-pin latchup in scaled-DRAM

Summary form only given. This paper describes a TCAD analysis of I/O-pin latchup failure found in a shallow-well CMOS DRAM. The 0.35 /spl mu/m DRAM I/O-pin showed significant degradation in latchup test of JEDEC Standard over-current stress. TCAD diagnosis of the failure was conducted and newly clarified the biasing effect of the guard-band (N/sup +/) layer and the layout-related latchup mechanism, which leads to a practical latchup-immunity design in sub-/spl mu/m CMOS process and layout. To overcome process-margin problem against latchup, a simple CMOS process is proposed for the 0.35 /spl mu/m DRAM.