Chieh Pin Chang

A Fully Integrated 5 GHz Low-Voltage LNA Using Forward Body Bias Technology

A fully integrated 5 GHz low-voltage and low-power low noise amplifier (LNA) using forward body bias technology, implemented through a 0.18 mum RF CMOS technology, is demonstrated. By employing the current-reused and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 10.23 dB with a noise figure of 4.1 dB at 5 GHz, while consuming only 0.8 mW dc power with a low supply voltage of 0.6 V. The power consumption figure of merit (FOM1) and the tuning-range figure of merit (FOM2) are optimal at 12.79 dB/mW and 2.6 mW-1, respectively. The chip area is 0.89times0.89 mm2.

A 3-dB Quadrature Coupler Using Broadside-Coupled Coplanar Waveguides

A 3-dB quadrature coupler which combines the advantages of broadside-coupling and coplanar waveguide structure suitable for a single-layer printed circuit board (PCB) circuit design is proposed. Compared to the recently published broadside-coupled structures, the proposed coupler can easily be realized in a single-layer substrate by using PCB manufacturing processes to eliminate the effects of uncertain factors from a multi-layer substrate. With the operation bandwidth ranging from 2.1 to 2.7 GHz, the measured return loss and isolation are all better than 19dB, and the insertion losses and relative phase difference between the direct and coupled ports are at 3.2 plusmn 0.1 dB and 90 plusmn 0.6deg, respectively. The dimension of the coupler is 2.1 cm times 1.9 cm.

A High Gain and Low Supply Voltage LNA for the Direct Conversion Application With 4-KV HBM ESD Protection in 90-nm RF CMOS

A 2.4-GHz low noise amplifier (LNA) for the direct conversion application with high power gain, low supply voltage and plusmn4 KV human body model (HBM) electrostatic discharge (ESD) protection level implemented by a 90-nm RF CMOS technology is demonstrated. At 12.9 mA of current consumption with a supply voltage of 1.0 V, the LNA delivers a power gain of 21.9 dB and the noise figure (NF) of 3.2 dB, while maintaining the input and output return losses below -11 dB and -18.3 dB, respectively. The power gain and NF are only 0.2 dB lower and 0.64 dB higher than those of LNA without ESD protection

A 10–40 GHz Broadband Subharmonic Monolithic Mixer in 0.18

A 10-40 GHz broadband subharmonic monolithic passive mixer using the standard 0.18 mum CMOS process is demonstrated. The proposed mixer is composed of a two-stage Wilkinson power combiner, a short stub and a low-pass filter. Likewise, the mixer utilizes a pair of anti-parallel gate-drain-connected diodes to achieve subharmonic mixing mechanism. The two-stage Wilkinson power combiner is used to excite a radio frequency (RF) and local oscillation (LO) signals into diodes and to perform broadband operation. The low-pass filter supports an IF frequency range from dc to 2.5 GHz. This proposed configuration leads to a die size of less than 1.1 times 0.67 mm 2 . The measured results demonstrate a conversion loss of 15.6-17.6 dB, an LO-to-RF isolation better than 12 dB, a high 2LO-to-RF isolation of 51-59 dB over 10-40 GHz RF bandwidth, and a 1 dB compression power of 8 dBm.

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A novel voltage controlled oscillation (VCO) topology using 90-m CMOS technology is demonstrated. The common-source PMOS single transistor integrated with an inductor leads to negative resistance for the VCO that minimizes the transistor size and decreases the flicker noise sources. To our knowledge, the topology of the core VCO is the most compact configuration ever reported. The fabricated VCO consumes 6.26mW with a supply voltage of 1 V and has a 1.68times1.41 mm2 chip area, including the ESD protection circuit. At 1.77 GHz, PMOS VCO features an output power in the range of -5.2 dBm, and exhibits a phase noise of -94 dBc/Hz at the offset frequency of 300 kHz and -107 dBc/Hz at 1MHz

m CMOS Technology

A novel post-linearization technique for fully integrated 5.5 GHz high-linearity LNA, implemented through a 0.18 mum RF CMOS technology, is demonstrated. The post-linearization technique adopts a folded cascode diode with a resistor and a capacitor in parallel as a third-order intermodulation distortion (IMD3) sinker. The LNA with the post-linearization technique has a +8.33 dBm IIP3, a power gain of 10.02 dB, and a noise figure of 3.05 dB, while consuming 6 mA from a supply voltage of 1.8 V. Comparison with the characteristics of the LNA without using post-linearization technique, the IIP3 is improved 6.21 dB, and the IMD3 can be reduced 12.77 dB. Moreover, the performances of noise figure and power consumption rise 0.09 dB and 0.08 mW, and the power gain lowers 0.3 dB after using the technique only. This technique indeed improves the linearity performance without obvious effects.

A Low Supply Voltage VCO Implemented by a Single Common-Source 90 nm CMOS Transistor

A novel configuration of double- balanced sub-harmonic mixer using a ring connected anti-parallel diode pair (RAPDP) is presented for operating in 26-30 GHz. The monolithic microwave integrated circuit (MMIC) was implemented with GaAs 0.15 mum PHEMT technology with the compact size of 0.85 x 0.85 mm2. The proposed mixer consists of two spiral transformer baluns and a band-reject filter. The RF spiral balun with a band-reject filter served by an L-C resonator is used to provide an output port for the IF extraction. The best conversion loss of the sub-harmonic mixer is 12.7 dB and LO-to-RF and LO-to-IF isolations are better than 24 dB and 28 dB respectively.

A Novel Post-Linearization Technique for Fully Integrated 5.5 GHz High-Linearity LNA

A new configuration of a balanced frequency PHEMT monolithic microwave integrated circuit doubler using open/short stub hybrids is proposed. With multi-coupled lines technology, the phase shifter is produced and applied to a Ka-band doubler successfully. As compared to the conventional lumped-element doubler, this phase shifter can make the doubler more compact in size and flexible in design. The doubler achieves an operation band width of 23 to 26 GHz with the best conversion loss of 7.4 dB at 25 GHz. In addition, the fundamental frequency suppression is better than 24.1 dB, and the chip dimension is as small as 0.85 times 1.1 mm2.

A Compact Ka-Band Doubly Balanced Sub-harmonic Mixer

Accumulating evidence indicates that oxidative stress contributes to the pathogenesis of acute lung injury (ALI). Previous studies have demonstrated that LPS-induced reactive oxygen species (ROS) mediates lung epithelial cell apoptosis. Fas/FasL signaling is an important cellular pathway in the induction of lung epithelial cell apoptosis in ALI.

A MMIC Doubler Based on Novel Open/Short Stub Hybrids

A newly proposed method, called the current-dependent hot-electron stresses, is used to study InGaP-gated and AlGaAs-gated low noise PHEMT devices with different drain currents at high drain voltage. The impact ionization between gate and drain is major mechanism affecting devices during hot-electron stressing, which are excited by the high gate-to-drain electric field. However, the measure of the effects of impact ionization related to the drain current, during the hot-electron stressing, is less discussed in the published literatures. In this work, the designed hot-electron stressed conditions, which are related to the different drain currents are used to demonstrate the influence of drain currents in hot-electron stresses and, furthermore, to estimate and compare InGaP-gated with AlGaAs-gated PHEMTs.