Chieh-Yang Chen

Process variation effect, metal-gate work-function fluctuation and random dopant fluctuation of 10-nm gate-all-around silicon nanowire MOSFET devices

In this work, process variation effect (PVE), work function fluctuation (WKF), and random dopant fluctuation (RDF) on 10-nm high-K/metal gate gate-all-around silicon nanowire MOSFET devices using full-quantum-mechanically validated and experimentally calibrated device simulation are studied. The small aspect ratio device has greater immunity of RDF, while suffers from PVE and WKF.

Optimal power consumption design of the amorphous silicon thin-film transistor gate driver circuit for 10.1-in. display panel manufacturing

In this paper, the dynamic characteristics of the novel amorphous silicon thin-film transistor gate drive circuit applied on a 10.1-in. panel are optimized by using a multi-objective optimization method. Simultaneously, considering the multiple electrical characteristics of the tested circuit, the achieved results reveal interesting properties as well as good sensitivity of the optimized design parameters. The optimal specifications not only suppress the output ripple, but also reduce the dynamic and static power consumptions.

Drain-induced-barrier lowering and subthreshold swing fluctuations in 16-nm-gate bulk FinFET devices induced by random discrete dopants

Management of process variation and random fluctuation is one of severe challenges in scaling down silicon-based devices continuously according to Moores law. Emerging fluctuation sources [1-3] consists of the most critical random dopant fluctuation (RDF) which degrade device characteristic significantly. Unfortunately, recent studies on RDDs were reported for SOI FinFETs [1,5,8]. In this work, we for the first time statistically study characteristic fluctuation of 16-nm-gate high-κ/metal gate (HKMG) bulk FinFETs with different aspect ratios (AR = 1 and 2; AR = Hfin/Wfin) by random-discrete-dopants (RDDs) inside silicon fin channel, based upon our recent simulation studies [1-2,4-7]. Randomly generated devices with three-dimensional (3D) RDDs inside device channel is incorporated into quantum-mechanically corrected 3D device simulation. We compared the DC characteristics for planar and bulk FinFET devices. For the N-type bulk FinFET with AR = 2, it has higher Ion and lower Ioff, further more the fluctuation of Ion and Ioff are both smaller than the results of planar one, and the fluctuation of threshold voltage (σVth) is 46.2 mV for the simulated N-MOSFETs which is significantly reduced to 22.9 mV for the bulk FinFET with AR = 2. We also discuss drain induced barrier lowering (DIBL) and subthreshold swing (S.S) for all devices, and the AR2 FinFET possesses the best performance no matter for the DIBL or S.S effects. There is 68.7% improvement on DIBL and 30.1% improvement on S.S from the planar [1,5,7-8] to AR2 FinFET. The findings of this study indicate that there is a relation between DIBL and RDDs position in which they are near or away from the silicon fin channel surface. It explains the different fluctuation magnitudes of the degraded DIBL effect on devices with the same number of RDDs.

Device Simulation–Based Multiobjective Evolutionary Algorithm for Process Optimization of Semiconductor Solar Cells

This article implements for the first time a numerical semiconductor device simulation-based multiobjective evolutionary algorithm (MOEA) for the characteristic optimization of amorphous silicon thin-film solar cells, based upon a unified optimization framework (UOF). To calculate the devices characteristic, a set of coupled solar cell transport equations consisting of the Poisson equation, the electron-hole current continuity equations, and the photo-generation model is solved numerically. Electrical characteristics, the short-circuited current, the open-circuited voltage, and the conversion efficiency are calculated to analyze the properties of the explored solar cells. The aforementioned device simulation results are used to evaluate the fitness score and access the evolutionary quality of designing parameters via the implemented non-dominating sorting genetic algorithm (NSGA-II) in the UOF. Notably, designing parameters including the material and structural parameters, and the doping concentrations are simultaneously optimized for the explored solar cells. The simulation-based MOEA methodology is useful in optimal structure design and manufacturing of semiconductor solar cells.

High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications

Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) Ion and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma etching (ICP). (4) Recorded high Ion/Ioff ratio and low subthreshold swing (S.S. ∼ 70 mV/dec.) of Ge n-FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.

Capacitance Characteristic Optimization of Germanium MOSFETs with Aluminum Oxide by Using a Semiconductor-Device-Simulation-Based Multi-Objective Evolutionary Algorithm Method

This paper, for the first time, optimizes the characteristics of capacitance–voltage (C–V) of germanium (Ge) metal-oxide-semiconductor field effect transistors (MOSFETs) with aluminum oxide (Al2O3) by using a semiconductor-device-simulation-based multi-objective evolutionary algorithm (MOEA) technique. By solving a set of 2D semiconductor device transport equations, numerical simulation is intensively performed for the optimization of the C–V curve of Ge MOSFET devices. To optimize the capacitance of Ge MOSFETs with respect to the applied voltage, by minimizing the total errors of the C–V curve between the device simulation and a given specification (and experimentally measured data), the thicknesses of Al2O3 and GeO2, the work function of gate electrodes, the distribution range of channel doping, the dielectric constants of Al2O3 and GeO2, and the source/drain doping concentration are considered in the process of optimization. The semiconductor device simulation and the MOEA method are integrated and performed based on a unified optimization framework. According to the sharp variation characteristics of the C–V curve, except for using a residual sum of squares (RSS) (i.e., the sum of squares of residuals) as an objective function, physical key parts of the curve are also considered in the optimization problem. The engineering results of this study indicate that the semiconductor-device-simulation-based MOEA method shows great performance to optimize the parameters, which not only minimize the objective values but also match the curve shape.

Multiobjective evolutionary approach to silicon solar cell design optimization

In this study, we implement a device simulation-based multi-objective evolutionary algorithm (MOEA) for the optimal design of silicon solar cells. The short-circuited current, the open-circuited voltage, and the conversion efficiency are calculated and used to evaluate the fitness score and access the evolutionary quality of designing parameters via the implemented non-dominating sorting genetic algorithm in the unified optimization framework. Designing parameters, the material and structural parameters are simultaneously optimized for the explored solar cells. Our device simulation-based MOEA methodology is useful, compared with the conventional genetic algorithm, in the solar cell design optimization.

Electrical characteristic and power consumption fluctuations of trapezoidal bulk FinFET devices and circuits induced by random line edge roughness

In this work, we use an experimentally calibrated 3D quantum-mechanically-corrected device simulation to study different types of line edge roughness (LER) on the DC/AC and digital circuit characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFETs. By using a time-domain Gaussian noise function as the LER-profile generator, we compare four types of LER: fin-LER inclusive of resist-LER and spacer-LER, sidewall-LER, and gate-LER for the trapezoidal bulk FinFETs. The resist-LER is most influential on characteristic fluctuation. For the same type, spacer-LER has at least 85 % improvement on σVth compared with resist-LER. As for the digital circuit characteristic, the rectangle-shape bulk FinFET has larger timing fluctuation.

Statistical device simulation of characteristic fluctuation of 10-nm gate-all-around silicon nanowire MOSFETs induced by various discrete random dopants

We study the impact of random dopant fluctuation (RDF) on electrical characteristics of 10-nm-gate high-κ/metal gate gate-all-around silicon nanowire MOSFET devices. To provide the best accuracy of device simulation, model parameters are validated by using full quantum mechanical simulation and calibrated with experimental results. Physical mechanism of RDs inside channel and penetration from the source/drain extensions into the channel is discussed. Electrical characteristic of the device is estimated with respect to different types of RDF.

Work function modulation of monolayer MOS 2 doped with 3d transition metals

Ever since the discovery of graphene, two-dimensional materials are promising to semiconductor industry. Monolayer molybdenum disulfide (MoS2) especially stands as a prospective candidate due to its stability in ambient environment; whereas, the direct bandgap makes it potential in electro-optical applications. Work function plays an important parameter for light-emitting diode and contact electrification [1-2]. Some studies [3-4] revealed magnetic properties of MoS2 by doping 3d transition metals, but the dependence of work function on adatoms remains vague. Under density functional theory (DFT) framework, the Perdew-Burke-Ernzerhof (PBE) exchange-correction functional is applied in Vienna ab initio Simulation Package (VASP). The cutoff kinetic-energy for the valence electron is 500 eV, where the convergence condition for the force acting on each atom is less than 0.01 eVÅ−1 and the energy difference is < 10−6 eV/cell. A 4×4 MoS2 supercell is modeled to simulate the adatom-MoS2 system, after the unit cell of MoS2 reaches equilibrium structure. The corresponding bandstructure and density of states are shown in Fig. 1, where the extracted bandgap of 1.71 eV agrees with the experiment [5]. For the supercell, the Brillouin zone for structural optimization is sampled using 2×2×1 k-points by Monkhorst-Pack algorithm. The vacuum space of 15 Å is maintained to avoid the interaction from another layer of MoS2. The dipole correction on the z-direction is considered for the electrostatic potential away from the surface and total energy.