Yu-Yu Chen

Optimal power consumption design of the amorphous silicon thin-film transistor gate driver circuit for 10.1-in. display panel manufacturing

In this paper, the dynamic characteristics of the novel amorphous silicon thin-film transistor gate drive circuit applied on a 10.1-in. panel are optimized by using a multi-objective optimization method. Simultaneously, considering the multiple electrical characteristics of the tested circuit, the achieved results reveal interesting properties as well as good sensitivity of the optimized design parameters. The optimal specifications not only suppress the output ripple, but also reduce the dynamic and static power consumptions.

Drain-induced-barrier lowering and subthreshold swing fluctuations in 16-nm-gate bulk FinFET devices induced by random discrete dopants

Management of process variation and random fluctuation is one of severe challenges in scaling down silicon-based devices continuously according to Moores law. Emerging fluctuation sources [1-3] consists of the most critical random dopant fluctuation (RDF) which degrade device characteristic significantly. Unfortunately, recent studies on RDDs were reported for SOI FinFETs [1,5,8]. In this work, we for the first time statistically study characteristic fluctuation of 16-nm-gate high-κ/metal gate (HKMG) bulk FinFETs with different aspect ratios (AR = 1 and 2; AR = Hfin/Wfin) by random-discrete-dopants (RDDs) inside silicon fin channel, based upon our recent simulation studies [1-2,4-7]. Randomly generated devices with three-dimensional (3D) RDDs inside device channel is incorporated into quantum-mechanically corrected 3D device simulation. We compared the DC characteristics for planar and bulk FinFET devices. For the N-type bulk FinFET with AR = 2, it has higher Ion and lower Ioff, further more the fluctuation of Ion and Ioff are both smaller than the results of planar one, and the fluctuation of threshold voltage (σVth) is 46.2 mV for the simulated N-MOSFETs which is significantly reduced to 22.9 mV for the bulk FinFET with AR = 2. We also discuss drain induced barrier lowering (DIBL) and subthreshold swing (S.S) for all devices, and the AR2 FinFET possesses the best performance no matter for the DIBL or S.S effects. There is 68.7% improvement on DIBL and 30.1% improvement on S.S from the planar [1,5,7-8] to AR2 FinFET. The findings of this study indicate that there is a relation between DIBL and RDDs position in which they are near or away from the silicon fin channel surface. It explains the different fluctuation magnitudes of the degraded DIBL effect on devices with the same number of RDDs.

Device Simulation–Based Multiobjective Evolutionary Algorithm for Process Optimization of Semiconductor Solar Cells

This article implements for the first time a numerical semiconductor device simulation-based multiobjective evolutionary algorithm (MOEA) for the characteristic optimization of amorphous silicon thin-film solar cells, based upon a unified optimization framework (UOF). To calculate the devices characteristic, a set of coupled solar cell transport equations consisting of the Poisson equation, the electron-hole current continuity equations, and the photo-generation model is solved numerically. Electrical characteristics, the short-circuited current, the open-circuited voltage, and the conversion efficiency are calculated to analyze the properties of the explored solar cells. The aforementioned device simulation results are used to evaluate the fitness score and access the evolutionary quality of designing parameters via the implemented non-dominating sorting genetic algorithm (NSGA-II) in the UOF. Notably, designing parameters including the material and structural parameters, and the doping concentrations are simultaneously optimized for the explored solar cells. The simulation-based MOEA methodology is useful in optimal structure design and manufacturing of semiconductor solar cells.

Multiobjective evolutionary approach to silicon solar cell design optimization

In this study, we implement a device simulation-based multi-objective evolutionary algorithm (MOEA) for the optimal design of silicon solar cells. The short-circuited current, the open-circuited voltage, and the conversion efficiency are calculated and used to evaluate the fitness score and access the evolutionary quality of designing parameters via the implemented non-dominating sorting genetic algorithm in the unified optimization framework. Designing parameters, the material and structural parameters are simultaneously optimized for the explored solar cells. Our device simulation-based MOEA methodology is useful, compared with the conventional genetic algorithm, in the solar cell design optimization.

Multi-objective Display Panel Design Optimization Using Circuit Simulation-Based Evolutionary Algorithm

We for the first time implement a multi-objective evolutionary algorithm (MOEA) to optimize the display panel gate driver circuits with amorphous silicon thin-film transistors (ASG driver circuit). The MOEA is integrated with a circuit simulator based upon a unified optimization framework. The results of this study indicate the developed optimization flow can find the better solutions than a simple GA. The measurement data of the fabricated sample further show the achieved result is robust and superior to the original design. This approach benefits design and manufacturing of display panels in the industry of information and communications technology.