Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Chien Chiang is active.

Publication


Featured researches published by Chien Chiang.


Thin Solid Films | 1995

Diffusion of copper through dielectric films under bias temperature stress

Gopal Raghavan; Chien Chiang; Paul B. Anders; Sing-Mo Tzeng; Reynaldo Villasol; Gang Bai; Mark Bohr; David B. Fraser

Abstract Copper diffusion in various dielectric films as a function of electric field and temperature is reported. In this study, we characterized the leakage current through various dielectric films as a function of electrical field and elevated temperature. Both electric field and temperature are observed to affect strongly the dielectric barrier lifetime. Nitride and oxynitride films are found to be much better barriers than thermal oxide while plasma TEOS had a much lower barrier lifetime. The activation energy of copper diffusion in thermal oxide is determined to be 1.2eV. A three-step model is proposed to explain the observed current—time characteristics. In the first stage, the applied bias causes the injection of positively charged copper ions into the dielectric. The lack of a neutralizing electron current results in space-charge build up which sets up an opposing field and reduces the ionic current. The second stage represents primarily the thermal diffusion of copper ions and neutral atoms. Finally, in the third stage, enhanced electric fields in the dielectric lead to breakdown.


Thin Solid Films | 1995

Crystallinity properties of parylene-n affecting its use as an ILD in submicron integrated circuit technology

X. Y. Zhang; S. Dabral; Chien Chiang; J.F. McDonald; Bin Wang

Parylene-n (Poly-p-xylylene) (PA-n) [1-3] has a long history of use as a moisture barrier for printed circuit boards and hybrids. This paper evaluates this compound as a candidate vapor-depositable polymer interlayer dielectric for submicron integrated circuit technology due to its low dielectric constant, good step coverage, and high etch selectivity. To apply PA-n on high-density very large scale integrated circuits, its properties, such as deposition rate, deposition yield, and crystallinity, are investigated as a function of deposition pressure and annealing temperature. The deposition rate was found in the range of 2.66 Pa to 13.3 Pa to be a linearly increasing function of pressure. Good-quality films were obtained when pressure was controlled below 10.64 Pa. Cloudy films, however, were found at 13.3 Pa. The deposition rate could be as high as 3.33 X 10 -10 m s -1 when deposited at 10.64 Pa. The plot of PA-n yield vs. pressure showed a constant plateau of 1 X 10 -4 m kg -1 from 2.66 Pa to 10.64 Pa. The optimum deposition rate was hence obtained at 10.64 Pa without compromising the deposition yield. The crystallinity-associated properties examined were hardness, dielectric constant, and water permeability. A lower deposition pressure was observed to produce higher crystallinity that could be further enhanced by thermal annealing. A 5 X 10 -8 m hard surface layer was detected with hardness 3.5 GPa, that was 3∼7 times larger than that of bulk hardness which was 0.4∼0.7 GPa. The bulk hardness was found to increase as crystallinity increased. The dielectric constant tended to increase when the deposition pressure decreased. Furthermore, the dielectric constant was nearly constant when the polymer was heated up to temperatures as high as 698 K. This behavior, together with the formation of the hard layer and a higher crystallinity, was believed to result from the improved film organization of the deposited films. The competition between the film build-up in the surface region and the monomer diffusion into the bulk region (penetration) was theorized to be responsible for the film organization. The water permeability, which was measured to be as low as 1.2 X 10 -15 kg m -1 s -1 Pa -1 and was found to increase as the deposition pressure was increased, further strengthened the film organization claim.


MRS Proceedings | 1992

Hardness and Modulus Studies on Dielectric Thin Films

Chien Chiang; Gabi Neubauer; Anne Sauter Mack; Ken Yoshioka; George Cuan; Paul A. Flinn; David B. Fraser

We report hardness and Youngs modulus measurements on various dielectric thin films. Hardness and modulus information was derived from indentation experiments with a Berkovich triangular-based diamond indenter in an ultra micro-indentation instrument (UMIS). We studied the effect of moisture content and phosphorous doping on hardness and Youngs modulus of low temperature Chemical Vapor Deposition (CVD) Si-oxides and found that dehydration and densification tend to harden samples, whereas increased P-doping results in a lower hardness. Hardness values of silicon nitride, silicon oxynitride, sputtered oxide, spin-on-glass and APCVD Si-oxides are compared. We also discuss how deposition conditions and chemical compositions correlate to dielectric properties such as stress as well as moisture uptake, thermal expansion coefficients and hardness and modulus values. Using these results, thermal stresses in encapsulated Al lines have been calculated and the calculated stress in Al is higher when encapsulated with dielectric films with higher moduli.


international ieee vlsi multilevel interconnection conference | 1989

Understanding of spin-on-glass (SOG) properties from their molecular structure

Chien Chiang; David B. Fraser

A summary of various types of SOG materials and their properties is presented. The authors correlate these properties with molecular structure and constituents such as phosphorous and methyl dopants. Process integration issues associated with each type of SOG material are also discussed.<<ETX>>


Seventh International IEEE Conference on VLSI Multilevel Interconnection | 1990

Electron cyclotron resonance (ECR) deposited SiO/sub 2/ films for interlayer dielectric application

Chien Chiang; David B. Fraser; D.R. Denison

Summary form only given. A study of ECR-CVD oxide for interlayer dielectric deposition is reported. Films have been characterized by various techniques such as stress, Fourier transform infrared (FTIR), etch rate, refractive index, breakdown field, and dielectric constant. The film properties and some process integration issues are discussed. C-V and I-V characteristics of an ECR-CVD deposited oxide indicate an 11-MV/cm breakdown field and 4.0 dielectric constant. Stress vs. temperature curves are shown for films deposited with substrate RF bias and without bias. A planar oxide surface on both a high-aspect-ratio gap and a contact topography is shown. As the RF bias increases, the deposition rate decreases, the Si-O peak width narrows, the film stress reduces, and the wet etch rate reduces. The threshold voltage shift caused by UV radiation when microwave power increases is shown.<<ETX>>


1989 Microelectronic Intergrated Processing Conferences | 1990

Electron Cyclotron Resonance CVD Planarization and Trench-Fill Processes

D. R. Denison; Chien Chiang; David B. Fraser

An electron cyclotron resonance (ECR) generated oxygen plasma has been used for the chemical vapor deposition (CVD) of Si02 by reacting the oxygen plasma beam with adsorbed silane. This study was done to define the process window for the deposition of planarized Si02 over metal interconnect topographies with aspect ratio (ratio of step height to gap width) of up to 3 to 1 and for silicon trench fill with aspect ratio up to 5 to 1. It is found that the ratio of resputter rate provided by rf bias on the substrate to the deposition rate, typically 20 to 55 percent, determines the maximum aspect ratio space that can be filled. The system parameters considered are silane flow rate, oxygen to silane flow ratio, rf bias power density, and microwave power.


international ieee vlsi multilevel interconnection conference | 1989

Interaction of metal with underlying dielectric films in multilevel interconnect systems

Chien Chiang; M. Lee; David B. Fraser; L.C. Yip; S. Mittal; K. Wu

The authors report the interaction of an aluminium film with its underlying LPCVD dielectric film. The LPCVD film absorbs moisture in the atmospheric environment and causes severe degradation in subsequently deposited metal films. The addition of phosphorus appears to have two competing effects: enhancement of water absorption and densification of the film. The authors have identified deposition temperature, plasma power density, and ion bombardment as parameters for improving dielectric film stability. Modifying the oxide network by doping the glass and/or providing energy during oxide deposition improves the dielectric integrity, and this type of stable dielectric film is very essential for a multilevel interconnect system.<<ETX>>


Archive | 1996

Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections

Chien Chiang; David B. Fraser


Archive | 1996

Method for forming multileves interconnections for semiconductor fabrication

Chien Chiang; David B. Fraser


Archive | 1999

Fabricating low K dielectric interconnect systems by using dummy structures to enhance process

Chien Chiang; David B. Fraser; Anne Sauter Mack; Jin Lee; Sing-Mo Tzeng; Chuanbin Pan; Vicky Ochoa; Thomas N. Marieb; Sychyi Fang

Collaboration


Dive into the Chien Chiang's collaboration.

Researchain Logo
Decentralizing Knowledge