David B. Fraser

Growth of epitaxial CoSi2 on (100)Si

A bilayer CoSi2/TiN has been grown on (100)Si, starting from a (100) p‐type Si wafer deposited with thin layers of Ti followed by Co metal, through a two‐stage annealing in a nitrogen environment and an intervening etch. In this process, Co and Ti switch places to form CoSi2 covered with TiN on Si. Cross‐section transmission electron microscopy, and Rutherford backscattering/channeling spectrometry were used to characterize the bilayer sample. The CoSi2 was found to be single crystal, fully coherent, and epitaxial with (100)Si, whereas the TiN at the top of CoSi2 was polycrystalline. The stress in the CoSi2/TiN layer was found to be 1.9×1010 dynes/cm2. The planar (100) CoSi2/Si interface was interrupted with {111} ledges which are believed to be structural ledges present to maintain the coherency at the interface.

Diffusion of copper through dielectric films under bias temperature stress

Abstract Copper diffusion in various dielectric films as a function of electric field and temperature is reported. In this study, we characterized the leakage current through various dielectric films as a function of electrical field and elevated temperature. Both electric field and temperature are observed to affect strongly the dielectric barrier lifetime. Nitride and oxynitride films are found to be much better barriers than thermal oxide while plasma TEOS had a much lower barrier lifetime. The activation energy of copper diffusion in thermal oxide is determined to be 1.2eV. A three-step model is proposed to explain the observed current—time characteristics. In the first stage, the applied bias causes the injection of positively charged copper ions into the dielectric. The lack of a neutralizing electron current results in space-charge build up which sets up an opposing field and reduces the ionic current. The second stage represents primarily the thermal diffusion of copper ions and neutral atoms. Finally, in the third stage, enhanced electric fields in the dielectric lead to breakdown.

Mechanical properties and microstructural characterization of Al-0.5%Cu thin films

Using a wafer curvature technique we have studied the variation of stress with tem-perature in Al-0.5%Cu thin films deposited on oxidized silicon wafers. Concurrently, the microstructural changes in the films induced by the thermal cycling inherent to this technique were studied with in-situ transmission electron microscopy heating experi-ments. On heating an as-sputtered film a stress drop occurs, corresponding to the onset of grain growth. The in-situ TEM experiments indicate that the extent of grain growth is significantly altered by the presence of compressive stresses in the film. During cool-ing, dislocation loops nucleate on {111} planes inclined to the film surface, although the grain size plays an important role in determining the extent to which this mechanism can account for the deformation. A native oxide can influence the stress levels in the film by pinning one end of the dislocation loops. Upon cooling below 200° C a rapid increase in stress occurs. Although this increase has been attributed to hardening due to the precipitation of excess copper, no evidence of precipitate-dislocation interactions were observed.

Formation of epitaxial CoSi2 on Si(100): Role of the annealing ambient

With a thin Ti layer interposed between a Si(100) substrate and a Co overlayer, the inversion of the Co and Ti films and the formation of a partly relaxed epitaxial CoSi2 layer on Si(100) can be obtained by steady‐state annealing in inert as well as reactive ambients. A reactive ambient chemically binds the Ti near the surface as an oxide or nitride layer, which preserves the bilayer structure during a high temperature treatment. In a nonreactive ambient, the Ti and CoSi2 layers react further, resulting in a uniform layer of Co0.25Ti0.75Si2 and CoSi2. An eptiaxial orientation of CoSi2 is retained even in that case.

Finite-element modeling and X-ray measurement of strain in passivated Al lines during thermal cycling

Narrow-pitch encapsulated Al lines are used as interconnect metallization in integrated circuits. The authors have measured the principal strain state of Al alloy lines passivated with silicon nitride directly as a function of temperature. They compare these results with calculations of the strain state in these lines using finite-element modeling. The measured strain-temperature behavior shows food fundamental agreement with finite-element modeling, although the magnitude of the strains measured with X-rays is less than that predicted by modeling due to voiding in the lines.

Anomalous behavior of shallow BF3 plasma immersion ion implantation

Plasma immersion ion implantation (PIII) with BF3 and SiF4 plasmas is used to fabricate shallow P+/N junctions in Si. Exposure to the plasma and accelerated ions can lead to simultaneous etching and deposition on the substrate during implantation. A simple mathematical model for this process is presented and applied to the case of shallow implantation of BF3. Etching rates of SiO2 are seen to vary with power and pressure of the process gas. Etching rates of Si, SiO2, and CoSi2 are studied by spectrophotometry and Rutherford backscattering spectrometry. The roughness of Si substrates and SiO2 and CoSi2 films before and after PIII is monitored by atomic force microscopy.

Low-temperature processing of shallow junctions using epitaxial and polycrystalline CoSi 2

Cobalt disilicide is grown epitaxially on (100) Si from a 15 nm Co/2 nm Ti bilayer by rapid thermal annealing (RTA) at 900°C. Polycrystalline CoSi2 is grown on (100) Si using a 15 nm Co layer and the same annealing condition. Silicide/p+-Si/n-Si diodes are made using the silicide as dopant source:11B+ ions are implanted at 3.5–7.5 kV and activated by RTA at 600–900°C. Shallow junctions with total junction depth (silicide plus p+ region) measured by high-resolution secondaryion mass spectroscopy of 100 nm are fabricated. Areal leakage current densities of 13 nA/cm2 and 2 nA/cm2 at a reverse bias of -5V are obtained for the epitaxial silicide and polycrystalline silicide junctions, respectively, after 700°C post-implant annealing.

In-Situ processing using rapid thermal chemical vapor deposition

Metal-Oxide-Semiconductor Capacitors (MOSCAP’s) were fabricated using Rapid Thermal Processing (RTP) techniques. MOSCAP’s that received in-situ polysilicon gate deposition after oxide growth evinced significantly tighter oxide breakdown voltage distribution as compared to devices that received ex-situ polysilicon deposition. Capacitance-Voltage (C-V) measurements of electrically unstressed and stressed devices indicate that the oxide charge, interface state density, electron trapping, and interface state generation characteristics are identical, irrespective of the mode of polysilicon gate deposition. It is concluded that, while in-situ processing may be capable of reducing particle related defects, no improvement is seen in the intrinsic properties of the oxide itself.

In situ x‐ray diffraction study of CoSi2 formation during annealing of a Co/Ti bilayer on Si(100)

X‐ray diffraction was performed in situ during annealing of a Co/Ti/Si(001) multilayer, which produced an epitaxial CoSi2 layer. The results indicate that the Ti layer did not stay intact during the reaction, and thus could not act like a membrane, moderating Co/Si interdiffusion. Strongly textured phases (M) formed prior to CoSi2 nucleation, and was unobservable upon completion of the anneal. Nucleation and growth of CoSi2 on Si(001) took place in the presence of M, new Co‐Ti‐(O) phases that were located at the metal/Si interface, and thus M might play an important role in the perfection of the silicide.

Comparison of cobalt and titanium silicides for SALICIDE process and shallow junction formation

A comparison of TiSi/sub 2/ and CoSi/sub 2/ for the SALICIDE (self-aligned silicide) process is presented. Both TiSi/sub 2/ and CoSi/sub 2/ are formed by RTA in nitrogen. The comparison is based on the formation kinetics, film properties, process compatibilities, and electrical properties. The results are summarized in table form. Co silicide is found to be a better candidate for use in SALICIDE process for submicron devices because it has a less severe lateral gate-S/D encroachment problem, less sensitivity to oxygen, higher resistivity to dry/wet etch, less film stress, better sheet resistance control, less junction leakage, the capability to form low-resistance polycide, and shallow junctions. However, substrate cleaning must ensure no SiO/sub 2/ on Si surfaces that are to be converted to CoSi/sub 2/.<<ETX>>