Chien-Chih Ho

Improved quality-factor of 0.18-/spl mu/m CMOS active inductor by a feedback resistance design

A novel CMOS active inductor approach, which can improve the quality-factor, was presented in this report. A cascode-grounded active inductor circuit topology with a feedback resistance was proposed, which can substantially improve its equivalent inductance and quality-factor. This feedback resistance active inductor was implemented by using a 0.18-/spl mu/m 1P6M CMOS technology, which demonstrates a maximum quality-factor of 70 with a 5.7-nH inductance at 1.55 GHz, where the self-resonant frequency is 2.5 GHz. The dc power consumption of this active inductor is less than 8 mW.

0.13-/spl mu/m RF CMOS and varactors performance optimization by multiple gate layouts

0.13-/spl mu/m radio frequency (RF) CMOS devices with multifinger gate structure have been fabricated by the standard logic process, and the measured effective gate-length is 80 nm. Extensive RF characterization has been done to obtain cutoff frequency (f/sub T/), associated power gain cutoff frequency (f/sub max/), minimum noise figure (NF/sub min/), output power (P/sub out/), and power added efficiency (PAE) for RF circuit design and to explore the optimized gate layout in terms of the extracted RF device parameters. Our important finding to be reported in this paper is that an optimized unit finger width (W/sub F/) exists by trade-off among f/sub T/, f/sub max/, NF/sub min/, P/sub out/, and PAE. Under fixed total width to achieve the same current drivability (I/sub ds/), the smaller W/sub F/ and the larger finger number (N/sub F/) leads to higher f/sub max/ but lower f/sub T/ due to trade-off between gate resistance (R/sub g/) and parasitic gate capacitance. As for NF/sub min/ complicated by f/sub T/ and R/sub g/, counter-balance between parasitic gate capacitance and R/sub g/ leads to nearly constant NF/sub min/ w.r.t. various splits of (W/sub F/,N/sub F/). Regarding P/sub out/ and PAE, W/sub F/ of 4 /spl mu/m and N/sub F/ of 18 is the optimized layout parameter, which offers the maximum P/sub out/ of around 11 dBm and PAE of 30.5% at 5.8 GHz. The performances of accumulation-mode MOS varactors with different gate layout structures are also investigated in this report. Since the same area varactors with different gate layout may result in different parasitic resistance and fringing capacitance, which will affect the capacitance tuning range and the associated Q-factor. The maximum Q-factor is about 59 of the 120 /spl mu/m/sup 2/ gate area varactor, and its tuning range is from 210 fF to 1.64 pF, where the maximum C/sub max//C/sub min/ ratio is about 7.8.

A fully integrated class-E CMOS amplifier with a class-F driver stage

This paper presents a fully integrated two-stage 1.9 GHz class-E amplifier, implemented by 0.18 /spl mu/m CMOS technologies. By using the switching operation mode of a class-E amplifier, the DC power dissipation can be reduced, and this amplifier delivers a 16.3 dBm output power at 1.9 GHz, with a maximum power-added efficiency (PAE) of 70% from a 2-V DC supply voltage. This monolithic amplifier includes the matching and biasing circuit, where no external components are required.

A 2.4 GHz low phase noise VCO fabricated by 0.18 /spl mu/m pMOS technologies

2.4 GHz monolithic voltage-controlled oscillators (VCOs) have been fabricated by 0.18 /spl mu/m pMOS technologies. A phase noise as low as -105 dBc/Hz at a 100 kHz offset is achieved in the output spectrum with a tuning range of 90 MHz, and the dc power consumption is 13.5 mW. Comparing with the nMOS VCO, the improved phase noise from the pMOS VCO is about 15 dB.

Scaleable large-signal model of 0.18 μm CMOS process for rf power predictions

Abstract The design of the radio frequency integrated circuits by CMOS technologies requires an accurate and scaleable model, which can be valid in the GHz range for device non-linear behavior predictions [IEEE Trans Solid State Circuits 35 (2000) 186; IEEE J. Solid-State Circuit 33 (1998) 1510]. A modified 0.18 μm gate-length MOSFET rf large-signal model based on BSIM3v3 is presented. This large-signal model includes the required parasitic components to forecast device dc and rf characteristics. Additionally, the microwave load-pull and digital modulated evaluations have been carried out to verify the accuracy of this model, where a good agreement with experimental results can be achieved.

Using auxiliary amplifier to cancel third-order intermodulation distortion for a 1.9 GHz CMOS linear amplifier design

A new linearization method for microwave amplifier design, by canceling the third-order intermodulation component, is proposed. The main amplifier is combined with an auxiliary amplifier, whose gain and bias conditions are appropriately designed. The output frequency spectra of the main amplifier are subtracted by this auxiliary amplifier. The third-order distortion is canceled since these two amplifiers are designed as a differential-pair stage. IIP/sub 3/ improvement as large as 11 dB has been obtained, where this amplifier achieves a 11.5 dB gain at 1.9 GHz, and is fabricated using 0.18 /spl mu/m CMOS technologies. The circuit consumed 11.5 mA or 11 mA for the auxiliary amplifier on or off, respectively. The auxiliary amplifier consumes less than 0.8 mW DC power and causes only 0.2 dB gain reduction of the main amplifier.

A fully integrated 2.4 GHz class-E amplifier with a 63% PAE by 0.18 μm CMOS technologies

Abstract A fully integrated 2.4 GHz class-E amplifier has been implemented by 0.18 μm CMOS technologies. By using the switching operating mode of a class-E amplifier, the dc power dissipation can be reduced. The amplifier delivers 17.3 dBm output power at 2.4 GHz, with a maximum power-added efficiency (PAE) of 63%, from a 2-V supply voltage. To ensure a stable performance of the device and circuit, the 0.18 μm MOSFET and the class-E amplifier also biased at high voltage stress for 150 h continuous testing. This monolithic amplifier includes the matching and biasing circuit, requiring no external components.

A fully integrated dual-band VCO by 0.18 μm CMOS technologies

Abstract A dual-band monolithic voltage-controlled oscillator (VCO) has been fabricated by using the 0.18 μm 1P6M CMOS technologies. The switching transistors concept used in the tank circuit realizes the dual-band VCO operation. In order to reduce the phase noise, the pMOS transistors were used in the VCO design. The dual-band VCO demonstrates the phase noise (100 kHz offset) of −98 dBc/Hz at 2.6 GHz and −91 dBc/Hz at 5.2 GHz.

A fully integrated 2.4 GHz RF transceiver by 0.18 /spl mu/m CMOS technologies

A fully integrated 2.4 GHz RF CMOS transceiver is presented in this report, which consumes 80 mW for the receiver operation, and 56 mW for the transmitter one. The transceiver was designed in an integrated form and fabricated by a 0.18 /spl mu/m standard CMOS process; all the matching networks and bias circuits were fabricated on the same chip. The receiver demonstrates a 7.5 dB conversion gain and the maximum output power of -5 dBm. The transmitter delivers a power gain of 18.5 dB, and the maximum output power of 12 dBm.

A 0.18 μm p-MOSFET large-signal RF model and its application on MMIC design

Abstract A modified 0.18 μm gate-length p-channel MOSFET large-signal rf model, based on the BSIM3v3 model, is presented in this report which achieves a good agreement with the device performance. This large-signal rf model includes the required passive components to fit the device dc and rf characteristics. To verify this modified model, the microwave load-pull and digital modulation evaluation have been conducted and compared them with the model predictions, where a good agreement has been reached for this 0.18 μm p-MOSFET. A 2.4 GHz fully integrated PMOS voltage-controlled oscillator (VCO) MMIC was designed based on this modified model. An accurate prediction of oscillation frequencies and output power levels of this 2.4 GHz PMOS VCO can be achieved, which demonstrates that the modified rf large-signal model can be applied for microwave circuit design.