Chin-Wei Kuo

A Novel Transmission-Line Deembedding Technique for RF Device Characterization

A novel transmission-line deembedding technique is presented in this paper. With this technique, the left- and right-side ground-signal-ground probe pads can be extracted directly using two transmission-line test structures of length L and 2L. An additional through structure is designed using via-stack deembedding, which is unique among current deembedding methods. The advantages of the proposed method include the following: 1) smaller silicon area; 2) discontinuity between the pad and interconnect; 3) substrate coupling and contact effects; and 4) employment of via-stack deembedding. The proposed novel methodology is a great breakthrough in the area of ultrahigh-frequency deembedding and should enable more accurate RF models to be developed. In the proposed methodology, intrinsic slow-wave CPW transmission-line structures are placed on the interlevel metallization layers, as they are the most appropriate RF device for cascade-based deembedding method involving the via-stack deembedding technique. Experimental results have demonstrated that attenuation loss and wavelength can be optimized by changing the metal density and the position of the metal layer on the floating shields. Both measurement and electromagnetic-wave simulations were performed up to 50 GHz. With a shortened wavelength, a reduction in silicon area of more than 66% can be achieved by using optimized slot-type floating shields.

TSV RF de-embedding method and modeling for 3DIC

TSV (Thru-Silicon-Via) for 3D packaging technique is a further passive component, for connecting two dies by stacking. RF characteristics of TSV with modeling up to 50GHz are presented in this paper, where a L-2L de-embedding method (double delay) is in use, which is the first applied for TSV on-wafer measurement. Furthermore, a new T-model is proposed for modeling a single TSV of 28nm CMOS process.

A Low-Flicker Noise Gate-Controlled Lateral–Vertical Bipolar Junction Transistor Array With 55-nm CMOS Technology

The low-flicker noise (1/f noise) gate-controlled lateral-vertical bipolar junction transistor array (GC-LV-BJTA) is developed with a foundrys 55-nm CMOS technology for low-noise and low-power RF circuit applications. The GC-LV-BJTA is formed by paralleling some unit cells into an array structure for sharing adjacent collectors and bases, thus minimizing the total area. Many efforts, including the use of a deep n-well, a novel layout, an optimized emitter perimeter/area ratio, and a negatively biased gate, have been implemented to suppress the noise level and enhance the current gain. As a result, the GC-LV-BJTA, consisting of 16 unit cells with a 0.16-μm gate length, achieves a high gain of 85.7 with available low 1/f noise level, as compared with the nMOS or SiGe HBT.

An extended de-embedding method for on-wafer components

On-wafer de-embedding method has been proposed for different method up to millimeter-wave (mm-wave) frequency range. An extended de-embedding method for on wafer devices up to 65 GHz is proposed. Using Vertical connection of L-2L (VL2L) is presented in this paper, with a calibrated loss tangent value in mm-wave. It shows significant good and accurate results for on-wafer modeling up to 65 GHz. VL2L are considered to be a good method for different kind of devices, such as capacitors. Also, the results by different CMOS process and EM simulation are with good agreement.