Chien-Chung Ho

How to enable software isolation and boost system performance with sub-block erase over 3D flash memory

The write amplification problem deteriorates as the block size of modern flash-memory chips keeps increasing. Without the careful garbage collection, significant live-page copying might even worsen the reliability problem, that is already severe to 3D flash memory. In this work, we propose a sub-block erase design to not only alleviate the write amplification problem by reducing live-page copying but also improve the system reliability with a software isolation strategy. In particular, sub-blocks are carefully allocated to satisfy write requests so as to reduce disturbance by using free or invalid sub-blocks as isolation layers among sub-blocks, without additional hardware cost and capacity loss. A series of experiments were conducted to evaluate the capability of the proposed design. The results show that the proposed design is very effective in improving the system performance by reducing garbage collection overheads and in improving the device reliability/lifetime.

Enabling sub-blocks erase management to boost the performance of 3D NAND flash memory

3D NAND has been proposed to provide a large capacity storage with low-cost consideration due to its high density memory architecture. However, 3D NAND needs to consume enormous time for garbage collection because of live-page copying overhead and long block erase time. To alleviate the impact of live-page copying on the performance of 3D NAND, a sub-block erase design has been designed. With sub-block erase design, this paper proposes a performance booster strategy to extremely boost the performance of garbage collection. As experimental results shows, the proposed strategy has a significant improvement on the average response time.

Antiwear Leveling Design for SSDs With Hybrid ECC Capability

With the joint considerations of reliability and performance, hybrid error correction code (ECC) becomes an option in the designs of solid-state drives (SSDs). Unfortunately, wear leveling (WL) might result in the early performance degradation to SSDs, which is common with a limited number of P/E cycles, due to the efforts to delay the bit-error-rate growth. In this paper, an anti-WL design is proposed to avoid such a performance problem so that the performance of SSDs with hybrid ECC capability can be improved without sacrificing their reliability. The capability of the proposed design was evaluated by a series of experiments, for which it was shown that the proposed design could greatly improve the read and write performance of SSDs up to 50% without affecting the endurance of the investigated SSDs, compared with traditional approaches.

A DRAM-flash index for native flash file systems

Index structures are widely used in file systems and database applications for efficient data management. This paper exploits the respective characteristics of DRAM and flash memory for tree index designs, for which a native file system is taken as an example target in the research. Different from DRAM caching or buffering of flash-memory access in the past work, a hybrid index design that resides over DRAM and flash memory simulaneously is proposed to improve system performance and space management. Tree nodes migrate between DRAM and flash memory, as needed, in response to user access pattern so as to optimize the performance and to reduce managing overhead. The capability of the proposed design is evaluated by a series of experiments, for which we have very encouraging results.

Rethinking I/O request management over eMMC-based solid-state drives

Due to its popularity and competitive prices, the embedded multimedia card (eMMC) has become a popular choice to replace raw flash chips in the design of solid-state drives (SSDs). However, an eMMC-based SSD often encounters its worst-case performance on random accesses. To address such a performance problem, this paper proposes an eMMC-aware strategy to exploit the characteristics of eMMC and access features of file systems, so as to effectively separate hot/cold data and repack data of I/O requests to improve the write performance of eMMC-based SSDs. According to the experiment results obtained, the proposed strategy can significantly improve random write performance, compared to prior works.

Access Pattern Reshaping for eMMC-enabled SSDs

The growing popularity of embedded Multi-Media Controllers (eMMCs) presents a unique opportunity to design commodity grade solid-state drives products. This work addresses the essential design issues of such drives and introduces a light-weight FTL design. In particular, access patterns to an eMMC-enabled solid-state drive are reshaped to create sequential access patterns and specific write sizes to better accommodate the characteristics of eMMCs, without resorting to the conventional address translation FTL design. At the same time, garbage collection overheads are minimized with reliability considerations, since eMMCs are usually not equipped with a powerful controller of a sophisticated design. The capability of the proposed design is evaluated by a series of experiments, for which we have very encouraging results.

A classification-based prefetching scheme for hibernation of embedded computing systems

With the rapid growth of embedded computing system markets, e.g., intelligent home appliances and smart TVs, vendors and researchers are developing more user-friendly interfaces and seeking to provide more sophisticated applications with better functionalities. Such a developing trend would prolong the initialization time of these embedded computing systems. Hibernation (or suspend-to-disk) that retains a computing systems state after power recycling is regarded as a solution to reduce the booting time of systems and applications to meet the requirement of user experiences. In contrast to the existing hibernation techniques that dump most of the memory pages to the secondary storage, we propose a classification-based prefetching scheme to improve the system performance on both of the hibernation and resuming with minimized I/O overheads by jointly considering the system/application behaviors and the usage patterns of memory pages. The proposed scheme was also implemented with the Linux kernel on an evaluation board to show the capability of the proposed scheme.

Block reinforcement to optimize lifetime of flash storage devices

With the advances of manufacturing technology and aggressive use of multi-level-cell (MLC) for flash memory, flash memory has faced a serious challenge on its device lifetime due to the fast-decreasing capacity caused by worn-out blocks. In contrast to existing works, we propose a block reinforcement scheme to optimize the guaranteed lifetime of flash storage devices by extending the useable period of flash blocks with limited performance degradation and space overhead. A serious of experiments was conducted to evaluate the efficacy of the proposed scheme and the results are very encouraging.

Current-aware scheduling for flash storage devices

As NAND flash memory has become a major choice of storage media in diversified computing environments, the performance issue of flash memory has been extensively addressed in many excellent designs. Among them, an effective strategy is to adopt multiple channels and flash-memory chips to improve the performance on data accesses. However, the degree of data access parallelism cannot be increased by simply increasing the number of channels and chips in the storage device, because it is seriously limited by the maximum current constraint of the bus interface and affected by the access patterns of user data. As a consequence, to maximize the degree of access parallelism, it is of paramount significance to have a proper scheduling strategy to determine the order that read/write requests are served. In this paper, a current-aware scheduling strategy for read/write requests is proposed to maximize the read performance without violating the bus current constraint and without missing (the deadline of) written data. The proposed strategy is then evaluated through a series of experiments, in which the results are quite encouraging.

Achieving defect-free multilevel 3D flash memories with one-shot program design

To store the desired data on MLC and TLC flash memories, the conventional programming strategies need to divide a fixed range of threshold voltage (Vt) window into several parts. The narrowly partitioned Vt window in turn limits the design of programming strategy and becomes the main reason to cause flash-memory defects, i.e., the longer read/write latency and worse data reliability. This motivates this work to explore the innovative programming design for solving the flash-memory defects. Thus, to achieve the defect-free 3D NAND flash memory, this paper presents and realizes a one-shot program design to significantly eliminate the negative impacts caused by conventional programming strategies. The proposed one-shot program design includes two strategies, i.e., prophetic and classification programming, for MLC flash memories, and the idea is extended to TLC flash memories. The measurement results show that it can accelerate programming speed by 31x and reduce RBER by 1000x for the MLC flash memory, and it can broaden the available window of threshold voltage up to 5.1x for the TLC flash memory.