Che-Wei Tsao

New ERA: new efficient reliability-aware wear leveling for endurance enhancement of flash storage devices

As the program/erase (P /E) cycles of flash memory keep decreasing, improving the lifetime/endurance of flash memory has become a fundamental issue in the design of flash devices. This work is motivated by the observation that flash blocks endured the same P/E cycles usually have different bit error rates. In contrast to the existing wear-leveling techniques that try to distribute erases to flash blocks as evenly as possible, we propose an efficient reliability-aware wear-leveling scheme to distribute block erases based on the bit error rates of blocks so as to even out the error rate among flash blocks, to maximize the number of good blocks, and thus to ultimately prolong the lifetime of flash storage devices. The experiments were conducted based on representative realistic workloads to evaluate the efficacy of the proposed scheme, for which the results are very encouraging.

Garbage collection and wear leveling for flash memory: Past and future

Recently, storage systems have observed a great leap in performance, reliability, endurance, and cost, due to the advance in non-volatile memory technologies, such as NAND flash memory. However, although delivering better performance, shock resistance, and energy efficiency than mechanical hard disks, NAND flash memory comes with unique characteristics and operational constraints, and cannot be directly used as an ideal block device. In particular, to address the notorious write-once property, garbage collection is necessary to clean the outdated data on flash memory. However, garbage collection is very time-consuming and often becomes the performance bottleneck of flash memory. Moreover, because flash memory cells endure very limited writes (as compared to mechanical hard disks) before they are worn out, the wear-leveling design is also indispensable to equalize the use of flash memory space and to prolong the flash memory lifetime. In response, this paper surveys state-of-the-art garbage collection and wear-leveling designs, so as to assist the design of flash memory management in various application scenarios. The future development trends of flash memory, such as the widespread adoption of higher-level flash memory and the emerging of three-dimensional (3D) flash memory architectures, are also discussed.

Performance enhancement of garbage collection for flash storage devices: an efficient victim block selection design

Motivated by the needs to enhance the performance of garbage collection in low-cost Hash storage devices, we propose a victim block selection design to efficiently identify the blocks for erases and reclaim the space of invalid data without extensively scanning Hash memory for the status of data stored in the storage, so as to achieve improved performance of garbage collection on reclaiming space of invalid data. At the same time, this design could also easily identify and reclaim the space released by file systems. A series of experiments based on benchmark traces demonstrates the significantly improved performance of garbage collection with limited system overheads.

A fifty-percent rule to minimize the energy consumption of PCM-based storage systems

In recent years, phase-change memory (PCM) has drawn a lot of attention because of its byte-addressability and non-volatility. It has become a good alternative storage medium to reduce the performance gap between main memory and secondary storage, but its high energy consumption on writes is a challenging issue in the design of battery-powered mobile computing systems. By utilizing the byte-addressability and the asymmetric read-write energy/latency of PCM, we propose an energy-efficient update scheme with a fifty-percent rule for journaling file systems to reduce the energy consumption. This scheme only writes the modified data, instead of the whole updated block, to PCM-based storage devices with the guarantee of the sanity/integrity of file systems even if the system crashes or power failure occurs during the process of data updates. A series of experiments based on the implementation on the Linux system was conducted to evaluate the capability of the proposed scheme, and the results are very encouraging.

Efficient Victim Block Selection for Flash Storage Devices

Motivated by the needs to enhance the performance of garbage collection in low-cost flash storage devices, we propose a victim block selection design to efficiently identify the blocks for erases and reclaim the space of invalid data without extensively scanning flash memory for the data status stored in the storage, so as to improve the garbage collection performance on reclaiming the space of invalid data. Moreover, this design could easily identify and reclaim the space released by file systems. Experiments based on benchmark traces show significant performance improvement of garbage collection with limited system overheads.

Rethinking I/O request management over eMMC-based solid-state drives

Due to its popularity and competitive prices, the embedded multimedia card (eMMC) has become a popular choice to replace raw flash chips in the design of solid-state drives (SSDs). However, an eMMC-based SSD often encounters its worst-case performance on random accesses. To address such a performance problem, this paper proposes an eMMC-aware strategy to exploit the characteristics of eMMC and access features of file systems, so as to effectively separate hot/cold data and repack data of I/O requests to improve the write performance of eMMC-based SSDs. According to the experiment results obtained, the proposed strategy can significantly improve random write performance, compared to prior works.

Block reinforcement to optimize lifetime of flash storage devices

With the advances of manufacturing technology and aggressive use of multi-level-cell (MLC) for flash memory, flash memory has faced a serious challenge on its device lifetime due to the fast-decreasing capacity caused by worn-out blocks. In contrast to existing works, we propose a block reinforcement scheme to optimize the guaranteed lifetime of flash storage devices by extending the useable period of flash blocks with limited performance degradation and space overhead. A serious of experiments was conducted to evaluate the efficacy of the proposed scheme and the results are very encouraging.

Proactive channel adjustment to improve polar code capability for flash storage devices

With the low encoding/decoding complexity and the high error correction capability, polar code with the support of list-decoding and cyclic redundancy check can outperform LDPC code in the area of data communication. Thus, it also draws a lot of attentions on how to adopt and enable polar codes in storage applications. However, the code construction and encoding length limitation issues obstruct the adoption of polar codes in flash storage devices. To enable polar codes in flash storage devices, we propose a proactive channel adjustment design to extend the effective time of a code construction to improve the error correction capability of polar codes. This design pro-actively tunes the quality of the critical flash cells to maintain the correctness of the code construction and relax the constraint of the encoding length limitation, so that polar codes can be enabled in flash storage devices. A series of experiments demonstrates that the proposed design can effectively improve the error correction capability of polar codes in flash storage devices.

A partnership-based approach to minimize the maximal response time of flash-memory storage systems

Multi-chip flash memory storage systems have been widely adopted in various applications, e.g., data centers. However, they have unpredictable maximal response time when garbage collection is triggered to reclaim space. This phenomenon becomes a critical issue in some applications that require storage systems offering predictable maximal response time to ensure some degree of quality-of-service. To resolve this issue, we propose a partnership-based approach to minimize the maximal response time of flash-memory storage systems by smartly controlling the number of flash chips performing garbage collection at the same time. This approach was evaluated with a series of experiments, and the results show that it could effectively minimize the maximal response time of flash-memory storage systems.

Distillation: A light-weight data separation design to boost performance of NVDIMM main memory

In the big data era, data-intensive applications have growing demand for the capacity of DRAM main memory, but the frequent DRAM refresh, high leakage power, and high unit cost bring serious design issues on scaling up DRAM capacity. To address this issue, NVDIMM, which is a hybrid memory module, becomes a possible alternative to replace DRAM as main memory in some data-intensive applications. NVDIMM that consists of a small-sized high-speed DRAM and a large-sized low-cost non-volatile memory (i.e., flash memory) has the serious performance issue on accessing data stored in the flash memory because of the huge performance gap between DRAM and flash memory. However, there is no or limited room to adopt a complex caching algorithm for using DRAM as the cache of flash memory in NVDIMM main memory because a complex caching algorithm itself would already cause too much performance degradation on handling each request to NVDIMM main memory. In this paper, we present a light-weight data separation design to boost NVDIMM performance with limited data separation overhead for reducing the data accesses to flash memory. A series of experiments was conducted based on popular benchmarks, and the results demonstrate that the proposed design can effectively improve the performance of NVDIMM main memory.