Chien-Min Huang

Efficient codebooks for vector quantization image compression with an adaptive tree search algorithm

This paper discusses some algorithms to be used for the generation of an efficient and robust codebook for vector quantization (VQ). Some of the algorithms reduce the required codebook size by 4 or even 8 b to achieve the same level of performance as some of the popular techniques. This helps in greatly reducing the complexity of codebook generation and encoding. We also present a new adaptive tree search algorithm which improves the performance of any product VQ structure. Our results show an improvement of nearly 3 dB over the fixed rate search algorithm at a bit rate of 0.75 b/pixel. >

Variable block size multistage VQ for video coding

In this paper, a video coding algorithm based on multistage vector quantization (MVQ) and rate distortion functions is proposed. Each frame is divided into 16/spl times/16 blocks. Each block is encoded using variable block size MVQ and/or block-based motion compensation. For the MVQ coding, each block is partitioned into blocks (or vectors) of size 256, 128, 64, 32, 16, and 8 pixels. The rate-distortion measurements associated with the different block sizes are used to select the partitioning of a particular block. The bit rate allocated to each frame depends upon a buffer fullness function as well as rate-distortion information for the frame. The proposed algorithm has low computational complexity for the decoder.

Locally optimal, buffer-constrained motion estimation and mode selection for video sequences

We describe a method of using a Lagrange multiplier to make a locally optimal trade off between rate and distortion in the motion search for video sequences, while maintaining a constant bit rate channel. Simulation of this method shows that it gives up to 3.5 dB PSNR improvement in a high motion sequence. A locally rate-distortion (R-D) optimal mode selection mechanism is also described. This method also gives significant quality benefit over the nominal method. Though the benefit of these techniques is significant when used separately, when the optimal mode selection is combined with the R-D optimal motion search, it does not perform much better than the codec does with only the R-D optimal motion search.

Very large scale integration (VLSI) implementation of block-based predictive Rice codec

This paper presents a VLSI implementation of the lossless block-based predictive Rice codec (BPRC). The BPRC uses an adaptive predictive coding algorithm to remove the redundancy in the image, codes the residue using an entropy coder. This algorithm can adapt well to local images statistics. The codec chip will encode 4 to 16-bit pixels at 10 Mpixels/sec input, and decode at 10 Mpixels/sec output. For images of normal size it requires little supports circuitry, only input data formatting and output data defomatting. Large images can be supported with external FIFOs.

Computation-efficient algorithms for image registration

Two computation-efficient algorithms are presented for automatically generating matching pixels for image registration. The first algorithm is an efficient Sequential Spatial Search Algorithm. A window selection and searching approach incorporated with a post-processing technique are used for restricting the image search area in order to increase reliability of pixel matching. The second method is the Hierarchical Fuzzy C-varieties-based algorithm. The translation and rotation between two images are estimated based on a combination of the closest match both in the centroid value and the membership count. Through a match-and- search procedure, the linear transformation is determined between images. Both methods resulted in good image mosaicking quality even for large rotation and translation.