Chiew-seng Koay

Evaluation of EUV resist materials for use at the 32 nm half-pitch node

The 2007 International Technology Roadmap for Semiconductors (ITRS)1 specifies Extreme Ultraviolet (EUV) lithography as one leading technology option for the 32nm half-pitch node, and significant world wide effort is being focused towards this goal. Readiness of EUV photoresists is one of the risk areas. In 2007, the ITRS modified performance targets for high-volume manufacturing EUV resists to better reflect fundamental resist materials challenges. For 32nm half-pitch patterning at EUV, a photospeed range from 5-30 mJ/cm2 and low-frequency linewidth roughness target of 1.7nm (3σ) have been specified. Towards this goal, the joint INVENT activity (AMD, CNSE, IBM, Micron, and Qimonda) at Albany evaluated a broad range of EUV photoresists using the EUV MET at Lawrence Berkeley National Laboratories (LBNL), and the EUV interferometer at the Paul Scherrer Institut (PSI), Switzerland. Program goals targeted resist performance for 32nm and 22nm groundrule development activities, and included interim relaxation of ITRS resist performance targets. This presentation will give an updated review of the results. Progress is evident in all areas of EUV resist patterning, particularly contact/via and ultrathin resist film performance. We also describe a simplified figure-of-merit approach useful for more quantitative assessment of the strengths and weaknesses of current materials.

Integration of EUV lithography in the fabrication of 22-nm node devices

On the road to insertion of extreme ultraviolet (EUV) lithography into production at the 16 nm technology node and below, we are testing its integration into standard semiconductor process flows for 22 nm node devices. In this paper, we describe the patterning of two levels of a 22 nm node test chip using single-exposure EUV lithography; the other layers of the test chip were patterned using 193 nm immersion lithography. We designed a full-field EUV mask for contact and first interconnect levels using rule-based corrections to compensate for the EUV specific effects of mask shadowing and imaging system flare. The resulting mask and the 0.25-NA EUV scanner utilized for the EUV lithography steps were found to provide more than adequate patterning performance for the 22 nm node devices. The CD uniformity across the exposure field and through a lot of wafers was approximately 6.1% (3σ) and the measured overlay on a representative test chip wafer was 13.0 nm (x) and 12.2 nm (y). A trilayer resist process that provided ample process latitude and sufficient etch selectivity for pattern transfer was utilized to pattern the contact and first interconnect levels. The etch recipes provided good CD control, profiles and end-point discrimination. The patterned integration wafers have been processed through metal deposition and polish at the contact level and are now being patterned at the first interconnect level.

Insertion strategy for EUV lithography

The first use of extreme ultraviolet (EUV) lithography in logic manufacturing is targeted for the 14 nm node, with possible earlier application to 20-nm node logic device back-end layers to demonstrate the technology. Use of EUV lithography to pattern the via-levels will allow the use of dark-field EUV masks with low pattern densities and will postpone the day when completely defect-free EUV mask blanks are needed. The quality of the imaging at the 14 nm node with EUV lithography is considerably higher than with double-dipole or double-exposure double-etch 193-nm immersion lithography, particularly for 2-dimensional patterns such as vias, because the Rayleigh k1-value when printing with 0.25 numerical aperture (NA) EUV lithography is so much higher than with 1.35 NA 193-nm immersion lithography and the process windows with EUV lithography are huge. In this paper, the status of EUV lithography technology as seen from an end-user perspective is summarized and the current values of the most important metrics for each of the critical elements of the technology are compared to the values needed for the insertion of EUVL into production at the 14 nm technology node.

EUV lithography at the 22nm technology node

We are evaluating the readiness of extreme ultraviolet (EUV) lithography for insertion into production at the 15 nm technology node by integrating it into standard semiconductor process flows because we believe that device integration exercises provide the truest test of technology readiness and, at the same time, highlight the remaining critical issues. In this paper, we describe the use of EUV lithography with the 0.25 NA Alpha Demo Tool (ADT) to pattern the contact and first interconnect levels of a large (~24 mm x 32 mm) 22 nm node test chip using EUV masks with state-of-the-art defectivity (~0.3 defects/cm2). We have found that: 1) the quality of EUVL printing at the 22 nm node is considerably higher than the printing produced with 193 nm immersion lithography; 2) printing at the 22 nm node with EUV lithography results in higher yield than double exposure double-etch 193i lithography; and 3) EUV lithography with the 0.25 NA ADT is capable of supporting some early device development work at the 15 nm technology node.

Modeling and experiments of non-telecentric thick mask effects for EUV lithography

Various issues related to non-telecentric mask effects for EUV lithography will be discussed in this paper. First, a raytracing approach will provide a conceptual description as to the nature of non-telecentric thick mask effects, highlighting the behavior of various edge types and corners. Rigorous modeling of these effects are discussed along with a few consequences of improper modeling. A series of simulation and experimental studies are presented to probe both the one- and two-dimensional impact of thick mask effects. It will be shown that a simple constant edge bias appears sufficient for 1D features, but begins to break down when space-widths are less than about 45 nm. Investigation into the impact of corners and small 2D features indicates that a simple edge-based bias also breaks down for edge lengths less than about 60nm. A sample set of rules-based post-OPC HV corrections for 22nm node dimensions are proposed, although based on experimental results, it is concluded that more accurate resist modeling and scanner stability are required before being able to precisely predict and control HV effects. Finally, with some simplifying assumptions, simulation is used to predict the extent of potential HV effects of future EUV imaging systems.

Overlay improvement roadmap: strategies for scanner control and product disposition for 5-nm overlay

To keep pace with the overall dimensional shrink in the industry, overlay capability must also shrink proportionally. Unsurprisingly, overlay capability < 10 nm is already required for currently nodes in development, and the need for multi-patterned levels has accelerated the overlay roadmap requirements to the order of 5 nm. To achieve this, many improvements need to be implemented in all aspects of overlay measurement, control, and disposition. Given this difficult task, even improvements involving fractions of a nanometer need to be considered. These contributors can be divided into 5 categories: scanner, process, reticle, metrology, and APC. In terms of overlay metrology, the purpose is two-fold: To measure what the actual overlay error is on wafer, and to provide appropriate APC feedback to reduce overlay error for future incoming hardware. We show that with optimized field selection plan, as well as appropriate within-field sampling, both objectives can be met. For metrology field selection, an optimization algorithm has been employed to proportionately sample fields of different scan direction, as well as proportional spatial placement. In addition, intrafield sampling has been chosen to accurately represent overlay inside each field, rather than just at field corners. Regardless, the industry-wide use of multi-exposure patterning schemes has pushed scanner overlay capabilities to their limits. However, it is now clear that scanner contributions may no longer be the majority component in total overlay performance. The ability to control correctable overlay components is paramount to achieving desired performance. In addition, process (non-scanner) contributions to on-product overlay error need to be aggressively tackled, though we show that there also opportunities available in active scanner alignment schemes, where appropriate scanner alignment metrology and correction can reduce residuals on product. In tandem, all these elements need to be in place to achieve the necessary overlay roadmap capability for current development efforts.

An Investigation of EUV Lithography Defectivity

We have used ASMLs full field step-and-scan exposure tool for extreme ultraviolet lithography (EUVL), known as an Alpha Demo Tool, to investigate one of the critical issues identified for EUVL, defectivity associated with EUV masks. The main objective for this work was to investigate the infrastructure currently in place to examine defects on a EUV reticle and identify their consequence in exposed resist. Unlike many previous investigations this work looks at naturally occurring defects in a EUV exposed metal layer from a 45 nm node device. The EUV exposure was also integrated into a standard process flow where the other layers were patterned using more conventional 193-nm lithography techniques. This presentation correlates reticle level defectivity to resulting wafer exposures. Defect inspection data from both the 28xx family of KLA-Tencor wafer inspection tool and Terascan reticle inspection tools are presented. Defect populations were characterized with a KLA 5200 Review SEM. Observed defectivity modes were analyzed using both conventional defect inspection methodology as well as advanced techniques in order to gain further insight. We find good correlations between reticle level defects and the resulting wafer exposure defects.

Are extreme ultraviolet resists ready for the 32nm node

The International Technology Roadmap for Semiconductors (ITRS) insertion point of extreme ultraviolet (EUV) lithography is the 32nm half-pitch node, and significant worldwide effort is being focused toward this goal. Potential road blocks have been identified and are being addressed. Readiness of EUV photoresists is one of the risk areas. According to the ITRS (www.itrs.net), a production-worthy EUV resist at 32nm half-pitch has to have a photospeed of ∼5mJ∕cm2 and line edge roughness (3σ) of 1.4nm. Toward this goal, the joint INVENT activity (AMD, CNSE, IBM, Micron, and Qimonda) at Albany has evaluated a broad range of EUV photoresists on various EUV exposure tools worldwide, including EUV MET at Lawrence Berkeley National Laboratory, EUV MET at SEMATECH Albany, and EUV interferometer at the Paul Scherrer Institute, Switzerland. This article will give a survey of the results, assessing the strengths and weaknesses of current materials.

Optimization of pitch-split double patterning phoresist for applications at the 16nm node

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

48nm Pitch cu dual-damascene interconnects using self aligned double patterning scheme

For sub-64nm pitch interconnects build, it is beneficial to use Self Aligned Double Patterning (SADP) scheme for line level patterning. Usually a 2X pitch pattern was printed first, followed by a Sidewall Image Transfer (SIT) technique to create the 1X pitch pattern. A block lithography process is then used to trim this pattern to form the actual designed pattern. In this paper, 48nm and 45nm pitch SADP build will be used as examples to demonstrate the SADP patterning scheme. General discussions about this patterning scheme will be provided including: 1) the process flow of this technique, 2) benefits of the technique vs. pitch split approach, 3) the design impact and limitation, and 4) the extendability to smaller line pitch build.