Chiewcharn Narathong

A CMOS VCO with 48% tuning range for modern broadband systems

This paper presents a CMOS VCO in a 0.35 /spl mu/m process which achieves a tuning range of 2.8 GHz-4.55 GHz and phase noise of -142dBc/Hz at 3 MHz offset (from a 1.8 GHz carrier). 5-bit digital coarse-tuning and accumulation-type MOS varactors allow for a 48% tuning range. An integrated regulator provides low supply pushing (100 kHz/V), reduces AM-to-PM sensitivity from the supply, and ensures optimum operation on multi-band/multi-standard single-chip transceivers with simultaneous operation. A model for the hand analysis of VCO noise is presented giving excellent agreement with measurements.

A highly-integrated tri-band/quad-mode SiGe BiCMOS RF-to-baseband receiver for wireless CDMA/WCDMA/AMPS applications with GPS capability

A 0.5 μm SiGe BiCMOS single-chip receiver integrates three front-ends (LNA, RF-to-IF mixer, VGA) for the cellular, PCS/IMT and GPS frequency bands, a shared I/Q demodulator, IF VCO, and UHF LO buffers. It has 2.0 dB NF and -0.6 dBm IIP3 in the cellular CDMA mode and 2.3 dB NF and -7 dBm IIP3 in the PCS mode with <150 mW at 3 V.

A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver, digital baseband and multimedia processor

Cellular phones in emerging markets have continued to grow with multimedia features such as MP3 playback, video encode and decode, high-resolution cameras and web browsing. To efficiently support multimedia functionalities, highperformance modems are required. There is also a strong demand to reduce the cellular phone PCB footprint, and to enable integration of peripheral devices such as Bluetooth and Wireless LAN. Previously reported SoC or SiP solutions have integrated a GPRS/EDGE radio with modem and limited multimedia capabilities [1–4]. This paper presents a multimode UMTS/GSM RF transceiver integrated with a digital baseband having advanced multimedia functionalities. The SoC, designed in 65nm digital CMOS, supports quad-band GSM/GPRS/EDGE (3GPP R4, Class 12) and tri-band UMTS/WCDMA (3GPP R99, R5 cat 5/6), including band 1–2–4–5–6–8–9–10.

A wideband CMOS VCO for zero-IF GSM-CDMA single-chip transceiver

This paper presents a low-power CMOS VCO in a 0.35 /spl mu/m process which achieves a tuning range of 2.47 GHz-3.47 GHz and phase noise performance of -145dBc/Hz at 3 MHz offset (from a 1.8 GHz carrier). 5-bit digital coarse-tuning and accumulation-type MOS varactors allow for a 33% tuning range, which is required to cover the LO frequency range of a zero-IF GSM-CDMA transceiver and to account for process and temperature variations. Optimum design techniques ensure low VCO gain (<104 MHz/V) for good interoperability with the frequency synthesizer. An integrated regulator provides low supply pushing (40 kHz/V) and reduces the AM-to-PM sensitivity from the supply.

A 65nm CMOS current controlled oscillator with high tuning linearity for wideband polar modulation

A highly linear oscillator is presented for wideband polar modulation. It has both varactor voltage tuning for frequency locking and temperature compensation as well as inductive current tuning for linear phase modulation. Implemented in 65nm CMOS, it achieved a gain variation less than ±2% over more than 32MHz range meeting WCDMA polar modulation requirement. At 3.8GHz and 3MHz offset, its phase noise is -136.5dBc/Hz with current consumption of 18mA from 2.1V supply.

A CMOS Highly Linear Hybrid Current/Voltage Controlled Oscillator for Wideband Polar Modulation

A highly linear oscillator is presented for wideband polar modulation. It has both a varactor voltage tuning input for frequency locking and temperature compensation of phase locked loop (PLL) as well as an inductive current tuning input for linear phase modulation of PLL. Implemented in 65 nm CMOS technology, it achieved a frequency tuning gain variation of less than ±2% over more than 32 MHz frequency range meeting the WCDMA polar modulation requirement. At 3.8 GHz and 3 MHz offset, its phase noise is -136.5 dBc/Hz with current consumption of 18 mA from 2.1 V supply.