Yiwu Tang

A novel wind-power generating system using field orientation controlled doubly-excited brushless reluctance machine

A novel variable-speed constant-frequency wind power generating system using a doubly-excited brushless reluctance machine is proposed. A field orientation control method is proposed to track the optimal torque-speed profile of the wind turbine and to realize flexible reactive power control. The proposed wind power generating system has the potentials of high efficiency, good flexibility, and low cost.<<ETX>>

Stator field oriented control of doubly-excited induction machine in wind power generating system

Optimal operation of a wind power generating system is featured by the variable-speed constant-frequency mode in which maximum-power capturing from the wind turbine and constant-frequency interfacing with the power system are the primary concerns. A slip power recovery system with a doubly excited wound rotor induction machine is attractive in this situation. Field orientation control for doubly excited induction machines is studied. Since the operational condition and control objectives of the variable-speed constant-frequency generating system are significantly different from those of a variable-speed drive system, the implementation strategy of field orientation control of induction machines must be reexamined. A stator field orientation control method suitable for the doubly excited induction machine in a wind power generating system is developed. Digital simulation was carried out showing that the doubly excited induction generator with the proposed control strategy can track the optimal torque-speed profile of a wind turbine very well. In addition, flexible reactive power control was also accomplished.<<ETX>>

A low-noise fast-settling PLL with extended loop bandwidth enhancement by new adaptation technique

A new adaptation scheme for low noise and fast settling phase locked loops (PLLs) is presented. Extended loop bandwidth enhancement is achieved by the adaptive control on the reference frequency and frequency divide ratio. It enables the loop bandwidth in the speed-up mode to greatly exceed the limit of approximately 1/10 of the channel spacing in the integer frequency synthesizer. Based on the proposed adaptation scheme, a 450 MHz frequency synthesizer with a 200 kHz channel spacing is implemented in 0.5 /spl mu/m CMOS process. In the speed-up mode, the loop bandwidth is enhanced by 16 times, resulting in a fast settling time of 260 /spl mu/s to within 20 kHz for a 72 MHz frequency step by simulation.

A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers

The loop bandwidth of PLL frequency synthesizers involves design tradeoffs between the lock time and reference feedthrough. The adaptive PLL solves the problem by increasing the bandwidth in the acquiring stage for faster lock speed and reducing the bandwidth after the loop locks for lower spur level. However, the loop bandwidth in the speedup mode is constrained to approximately 1/10 of the reference frequency for stability considerations. In this paper, the theoretical bandwidth limitation is explored with a simple nonlinear sampling delay model. A new adaptation scheme is proposed that extends the loop bandwidth enhancement by adaptively controlling the reference frequency in a gear-shifting approach. In the speedup mode, the loop bandwidth is enhanced by up to 64 times due to the increased reference frequency, resulting in a fast settling time of 229 /spl mu/s to within 20 kHz for a 80 MHz frequency step in a 200 kHz channel spacing synthesizer.

A fully integrated dual-mode frequency synthesizer for GSM and Wideband CDMA in 0.5/spl mu/m CMOS

A fully integrated dual-mode frequency synthesizer for GSM and Wideband CDMA (WCDMA) is presented. The synthesizer is designed to maximize hardware sharing between the two modes by applying fractional frequency synthesis to GSM mode and integer frequency synthesis to WCDMA mode. The shared components include phase frequency detector (PFD), charge pump (CP), loop filter, integer frequency divider and VCO, which is 70% of the entire synthesizer in term of die area. A high-speed low power dual modulus prescaler is proposed to operate up to 2.1GHz at 3.3V supply voltage with 11.6mW power consumption by simulation. A dual mode VCO is also proposed for the enhanced tuning range with an accumulation mode NMOS varactor for band-to-band tuning and a p/sup +/n junction varactor for in-band tuning. The simulation result shows that the synthesizer phase noise is -112dBc/Hz at 600kHz offset frequency for WCDMA mode and -117 dBc/Hz for GSM mode.

A new converter topology for advanced static VAr compensation in high power applications

Two genetic configurations of forced commutated PWM (pulse-width-modulated) converters, i.e., voltage source inverters and current source inverters, have been proposed as advanced reactive power compensators. A new configuration combining the features of the two generic ones is proposed and analyzed in the present work. It is composed of a PWM current source inverter handling high power with very low switching frequency, and a PWM voltage source harmonic filter handling low power with a much higher switching frequency. The result is that switching losses and harmonic distortions are minimized simultaneously.<<ETX>>

The Chip. A methodology for fast SPICE simulation of frequency synthesizers

Welcome to the Chip! Last year in the January issue of this magazine, the problem of simulating a sigma-delta modulator at the transistor level using SPICE was discussed and a simulation flow presented that could speed up simulation time significantly while keeping the accuracy almost intact. Transistor-level simulation is a must for optimizing the design at the final stages. In this column, we discuss a flow for the fast simulation of phase-lock loops, another widely used mixed-signal feedback system where transistor-level simulation is prohibitive. in the article, we discuss a mixed-mode methodology that uses macromodels for the digital parts while keeping the critical analog parts at the transistor level. We show that the method is effective and maintains very high accuracy.

Stability analysis of a slip power recovery system under open loop and field orientation control

The slip power recovery configuration provides an attractive alternative for variable speed drives and generating systems, due to its high-efficiency and low converter rating. The core component is the doubly-excited machine. The authors present a stability analysis of the doubly-excited machine with open-loop voltage and open-loop current control in the rotor circuit. The possibilities of open loop control are analyzed. The authors then present a unified model of a high-performance slip power recovery system comprising a field-orientation controlled doubly-excited machine, power converters, and a DC bus in the rotor circuit. The stability of this composite system is also studied. Of special interest is when the system functions as a variable-speed motor or as a variable-speed constant-frequency generating system. It is concluded that, under certain conditions, rotor open-loop voltage and current control are both stable for both motor and generator operations. The field orientation process is stable if the computation is fast enough or if there is additional compensation.<<ETX>>

A High-Speed Low-Power Divide-by-15/16 Dual Modulus Prescaler in 0.6 μm CMOS

A new high-speed low-power dual modulus prescaler (DMP) topology is proposed. In this DMP, the synchronous part is designed as a divide-by-3/4 divider using a state-selection scheme. Compared with the conventional divide-by-4/5 divider, it has a higher speed by eliminating the NAND-gate introduced critical path delay, as well as a lower power consumption by minimizing the number of full-speed D-type flip-flops (DFFs) required. Based on this topology, a divide-by-15/16 DMP is implemented in the 0.6 μm standard CMOS process. Simulation result shows that a maximum operating frequency of 2.15 GHz is obtained at 3.3 V supply with a power consumption of 11.6 mW. The circuit can operate above 3 GHz with 5 V supply and down to 1.5 V supply voltage with 570 MHz input frequency.