Chih-Chan Tu

Analog front-end amplifier for ECG applications with feed-forward EOS cancellation

This paper presents a low-noise low-power Instrumentation Amplifier (IA) for ECG applications. Chopped capacitively-coupled IA (CCIA) is built to precisely define the gain and avoid flicker noise. The circuit for electrode offset (EOS) cancellation is implemented in feed-forward (FF) manner with an area-efficient SC integrator. The FF architecture uses less capacitor ratio to define the low HPF corner than the feedback architecture. Implemented in a 0.18-μm process, the circuit draws 4.2 μA from a 1.8 V supply, and occupies 0.63mm2. The total integrated noise from 0.5 to 100Hz is 7.37 μVrms.

Measurement and parameter characterization of pseudo-resistor based CCIA for biomedical applications

This paper performs the detailed analysis and measurement of a pseudo-resistor based CCIA used for bio-potential signal acquisition. The pseudo-resistor is implemented with MOS transistors operating in deep sub-threshold region, whose characteristic is not well-modeled in simulation. The resistor value versus control voltage and the effect of leakage current at OPAMP input node are discussed and characterized in this paper. The tested chip consumes 1.3μA from a 1-V supply, and the total integrated noise from 0.5 to 100 Hz is 3.26μVrms. It achieves a noise efficiency factor of 14.6.

A 0.06mm 2 ± 50mV range −82dB THD chopper VCO-based sensor readout circuit in 40nm CMOS

A VCO-based sensor readout circuit is presented. It comprises a VCO-based integrator with counters, and a capactively-coupled feedback DAC, to form a 1st-order DSM with high input impedance and wide dynamic range for voltage sensors. Chopping is applied to suppress the flicker noise. The time-domain approach relaxes the voltage swing requirement compared to that of a Gm-C integrator, and thus area efficiency is achieved. The prototype is implemented in 40nm CMOS. It consumes 21μA under 1.2V supply. With a 100mVpp sinusoidal input, it achieves 74.9dB SNDR over 2 kHz BW and the THD is −82dB. This readout circuit is also measured with a Hall sensor to demonstrate its operation. The FoM and distortion achieves the state-of-the-art performance of VCO-based sensor readout circuits.

An area-efficient wideband CMOS hall sensor system for camera autofocus systems

This paper presents an area-efficient and fast-response CMOS Hall sensor system for a camera autofocus system. The prototype comprises of a Hall sensor and a capacitively-coupled instrumentation amplifier (CCIA). The Hall sensor adopts the spinning current technique to mitigate the Hall element offset. In the CCIA, the T-capacitor network is employed considering the capacitor matching requirement and the chip area. The amplifier offset is further suppressed by a ripple-reduction loop. This chip is measured with Helmholtz coil, Solenoid, and NMR system. Implemented in a 0.18-μm CMOS process, it achieves 564 μTrms in 180-kHz BW. The linearity error is < 0.5% over ±100-mT range. The power consumption is 1.19 mW, and the area is 0.12 mm2.

A 40-nV/VHz 0.0145-mm 2 sensor readout circuit with chopped VCO-based CTDSM in 40-nm CMOS

A sensor readout circuit employing chopped VCO-based CTDSM is presented in this paper. This VCO-based ADC features direct connection to the sensors to eliminate pre-amplifier. The VCO is designed as a Gm-CCO, which is a Gm stage cascaded with the folded-cascode current-controlled oscillator. The proposed circuit ensures a high input impedance. Furthermore, the main noise and offset contributor, the Gm stage, is mitigated by chopping operation. The VCO-based CTDSM is implemented in 40-nm CMOS. The whole circuit draws 14 μA from 1.2-V supply. With a 2.4-mVpp input, it achieves 49.43 dB SNDR over 5-kHz BW and has SFDR of 59.5 dB. The input-referred noise is 40nV/√Hz. The chip area is only 0.0145 mm2.

A 135-μW 0.46-mΩ/√Hz thoracic impedance variance monitor with square-wave current modulation

A low-power high-resolution thoracic impedance variance (TIV) monitoring circuit is presented. The TIV information is extracted by injecting a square-wave modulated current to the body. The resulted voltage is then demodulated by a proposed delayed-sampling technique. This proposed technique solves the gain-error issue occurred in prior square-wave modulated architectures. Furthermore, compared with sine-wave modulation, the proposed TIV monitoring circuit is more power efficient. Fabricated in a 0.18-μm CMOS, this chip draws 75 μA from a 1.8-V supply. The equivalent input-referred impedance noise density is only 0.46 mΩ/VHz.

An area-efficient capacitively-coupled instrumentation amplifier with a duty-cycled Gm-C DC servo loop in 0.18-μm CMOS

A chopped capacitively-coupled instrumentation amplifier (CCIA) with a proposed duty-cycled Gm-C DC servo loop (DSL) for bio-potential signal acquisition is presented. The proposed architecture realizes a large time constant with small circuit area without sacrificing noise and power performance. Furthermore, this pseudo-resistor-less design grants this architecture easily portable for more advanced processes. Fabricated in a 0.18-μm CMOS, this chip draws 2.37 μA from a 1.8-V supply and occupies only an active area of 0.43 mm2. The total integrated noise from 0.5 to 100 Hz is 1.04 μVrms and results in a noise efficiency factor of 7.8.