Chih-Hsien Lin

4/2 PAM serial link transmitter with tunable pre-emphasis

In this paper, we will implement a 4/2 PAM transmitter of the high-speed data serial link over cable and demonstrate a new development of the pre-emphasis circuit. The overall circuit is implemented in TSMC 0.18/spl mu/m P6M 1.8V CMOS process. The performance of the transceiver can reach 20/10 Gbps over the 1-5 meter long cable.

Design and analysis of digital data recovery circuits using oversampling

A performance evaluation and circuit architecture for all-digital data recovery using an oversampling method is proposed. The architecture is very regular and hence very suitable for standard-cell implementation flow. Due to its feedforward architecture, the required bit-rate can be achieved through proper pipelining. These properties make the proposed architecture very suitable as soft silicon intellectual property. Analysis of BER due to the combined effects of the key design parameters like data jitter, clock jitter and oversampling ratio in the oversampling technique are carried out. Thus different specifications of data recovery can be designed with different design parameters. A module generator that can estimate the design parameters automatically is established. Design implementation shows the proposed all-digital data recovery circuit can achieve 3.07 Gbit/s (post-layout) with 0.25 µm 2.5 V CMOS technology standard-cell design and occupies 380×390 µm2 chip area.

4/2 PAM Pre-emphasis Transmitter with Combined Driver and Mux

A new multi-Gbps pre-emphasis design methodology and circuits for a 4/2 PAM transmitter over cable are proposed. Theoretical analysis of the total frequency response of pre-emphasis, package, cable and termination are carried out. Then, we propose a pre-emphasis design method so that the over all frequency response in the receiver side is uniform within the desired frequency range. A test chip of transmitter with pre-emphasis, PLL circuit and on-chip termination resistors are implemented to verify the design methodology. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results

Multi-gigabit pre-emphasis design and analysis for serial link

In this paper, a multi-Gbps pre-emphasis design methodology and circuits for a 4/2 Pulse Amplitude Modulation (PAM) transmitter of high-speed data serial link over cable are proposed. Theoretically analysis of the total frequency response including pre-emphasis, package, cable loss and termination are first carried out. In order to gain higher data rates without increasing of symbol rate, we use 4 PAM in our system. Then, we propose a pre-emphasis architecture and algorithm that can enlarge the high frequency response so the overall frequency response in the receiver side is uniform within the desired frequency range. The overall circuit is implemented in TSMC 0.18μm 1P6M 1.8 V CMOS process. A test chip of this transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented by full custom flow to verify the design methodology. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (in) long cable and is in agreement with our analysis and simulation results.

Module generator of data recovery for serial link receiver

A module generator for the all-digital data recovery of a highspeed serial link, using an oversampling method, is proposed. The architecture of the proposed method is very regular and hence very suitable for standard cell implementation flow, which also makes it very suitable as a soft silicon intellectual property. This module generator can automatically generate the design parameters to deal with the oversampling architecture to meet different specifications. A design example, generated by the module generator, is implemented by using the TSMC 0.35 /spl mu/m 1P4M cell library. The maximum performance of the design (without extra pipelining stages) can reach 2.09 Gbps with power consumption of 112.2 mW at 3.3 V.

A micro-network on chip with 10-Gb/s transmission link

In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13μm CMOS technology. The core area of this chip is 990μm∗1600μm and the power consumption is 155mW (60mW for micro-switches and 95mW for 10-Gb/s data transceiver) at 1.2V supply voltage with 10-Gb/s transmission data rate.

DC-Balance Low-Jitter Transmission Code for 4-PAM Signaling

This investigation proposes a novel dc-balanced low-jitter transmission code, a 4-PAM symmetric code, for a 4-PAM signaling system. The 4-PAM symmetric code preserves all of the useful characteristics of the 8B/10B code such as dc-balanced serial data and guaranteed transitions in the symbol stream for clock recovery. Moreover, the proposed method decreases the jitter of the timing transition of the data in the receiver and consumes half of the data bandwidth, because it transmits in 4-PAM. The design results using the UMC 0.18-mum process demonstrate that the new transmission code can decrease the jitter of the transition point by plusmn25%; of the transition region. The operation speed of the encoder/decoder for the 4-PAM symmetric code is 819 MHz with 16-b inputs (13.1 Gb/s) and 704 MHz with 16-b outputs (11.3 Gb/s)

Multi-gigabit serial link transmitter - off-chip and on-chip

Multi-Gbps serial link transmitter for both off-chip and on-chip transmission are presented. For off-chip transmission, a new pre-emphasis design methodology and circuits for a 4/2 PAM transmitter over cable are proposed. A test chip of transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented using tsmc 0.18 um CMOS process. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results. For on-chip transmission, SerDes based serial link architecture is used in on-chip application. Using tsmc 0.13 um CMOS process, the operation speed and power consumption are 5 Gbps and 3.2 mW respectively with the interconnect area is half of parallel architecture.