Chauchin Su
National Chiao Tung University
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Chauchin Su.
international test conference | 1993
Chauchin Su; Kychin Hwang
This paper presents a serial scan test vector compression methodology for the test time reduction in a scan-based test environment. The reduction is achieved by the overlapping of two consecutive vectors. Hence, the order of test vectors determines the amount of reduction in tiem. Here, two test vector ordering algorithms, depth first greedy and coalesced simple orders algorithms, have been derived, implemented, and tested. Experimental results obtained are very close to estimations by statistical analysis.<<ETX>>
IEEE Journal of Solid-state Circuits | 1997
Shyh-Jye Jou; Chang-Yu Chen; En-Chung Yang; Chauchin Su
This paper proposes a new pipelined full-adder circuit structure for the implementation of pipelined arithmetic modules. With both static and dynamic structures, it has the advantages of high operational speed, smallest transistor count, and the low power/speed ratio. The adder cell is then used to design a pipelined 8/spl times/8-b multiplier-accumulator (MAC). In this MAC, a special pipelined structure is designed to reduce the latency. The MAC is fabricated in a 0.8-/spl mu/m single-poly-double-metal CMOS process. The post-layout simulation shows that the pipelined 1-b full adder can work up to 350 MHz with a 3 V power supply. The whole MAC chip that contains 4200 transistors is measured to operate a 125 MHz using 3.3 V power supply.
IEEE Transactions on Biomedical Circuits and Systems | 2012
Yuhwai Tseng; Yingchieh Ho; Shuoting Kao; Chauchin Su
This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 μm CMOS technology with a core area of 0.77 × 0.36 mm2. With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09 μW , respectively.
asia and south pacific design automation conference | 2005
Katherine Shu-Min Li; Chung Len Lee; Chauchin Su; Jwu E. Chen
We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and crosstalk glitches. IEEE P1500 wrapper cells are modified. An efficient ring-generation algorithm is proposed to construct ORs based on a graph model. Experimental results on MCNC benchmark circuits show the feasibility of the scheme and the effectiveness of the algorithm. Our method achieves 100% fault coverage with a small number of tests.
design, automation, and test in europe | 2000
Chauchin Su; Yue-Tsang Chen; Mu-Jeng Huang; Gen-Nan Chen; Chung-Len Lee
This paper proposes an all digital on-chip bus delay and crosstalk measurement methodology. A diagnosis procedure is derived to distinguish the delay faults in drivers, receivers, and wires. The crosstalk profile is plotted by monitoring the changes in delay with the presence of the crosstalk. The distinguished features include all digital design and low hardware overhead. The SPICE simulation results prove the feasibility of the methodology.
IEEE Transactions on Circuits and Systems | 2009
Hungwen Lu; Chauchin Su; Chien-Nan Jimmy Liu
This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show that the proposed design can achieve higher bandwidth and be less sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18- mum CMOS technology. Measured results indicate that the proposed design can operate up to 7 gigabits/s under 0.3-UI jitter limitation.
IEEE Transactions on Circuits and Systems Ii-express Briefs | 2012
Yingchieh Ho; Chiachi Chang; Chauchin Su
This brief presents a bootstrapped CMOS inverter operated with a subthreshold power supply. In addition to improving the driving ability, a large gate voltage swing from -VDD to 2VDD suppresses the subthreshold leakage current. As compared with other reported works, the proposed bootstrapped inverter uses fewer transistors operated in the subthreshold region. Therefore, our design has shorter delay time. The Monte Carlo analysis results indicate that a sigma of delay time is only 6.3 ns under the process and temperature variations with 200-mV operation. Additionally, a test chip is fabricated in the 90-nm SPRVT low-K CMOS process. Chip measurement results demonstrate the feasibility of operating ten-stage bootstrapped inverters with a 200-fF loading of each stage at 200-mV VDD. The test chip is able to achieve 10-MHz clock rate at 200 mV VDD, the power consumption is 1.01 μW, and the leakage power is 107 nW.
symposium on vlsi circuits | 2012
Shu Yu Hsu; Yingchieh Ho; Yuhwai Tseng; Ting You Lin; Po Yao Chang; Jen Wei Lee; Ju Hung Hsiao; Siou Ming Chuang; Tze Zheng Yang; Po Chun Liu; Ten Fang Yang; Ray Jade Chen; Chauchin Su; Chen Yi Lee
A multi-functional cardiac signal processor (CSP) with integrated sensor interfaces is designed for mobile healthcare applications, especially for heart activity diagnosis in different phases. Applying dedicated processing engines, the CSP extracts critical cardiac signal features based on compressed data with 90% storage reduction, while keeping the data network secure. Implemented in 90nm CMOS, the CSP consumes 22.6μW to 46.5μW at 0.5/1.0V in different configurations. Besides, the 10.2μW biopotential and 11.4μW capacitive sensor interfaces further enhance the system functionality.
international test conference | 2001
Chauchin Su; Wenliang Tseng
Three-state drivers are modified to exhibit wired-logic properties in test mode. It does not only make interconnects random pattern testable but also improves the fault coverage and shortens the test length simultaneously.
international symposium on circuits and systems | 1993
Chiyuan Chang; Chauchin Su
A methodology for the design and implementation of an universal interconnect built-in self test module for boundary-scan-based interconnects is proposed. Such a methodology is able to test any interconnects without knowing their connection configuration in advance. The fault-free responses of different I/O ports under the selected walking sequence of ones are studied. The faulty syndromes are enumerated for different faults, and compared with the fault-free ones. Two verification criteria are derived to verify the correctness of the nets. A universal interconnect (UI)-BIST hardware is designed, implemented, and tested.<<ETX>>