Chih-Ting Yeh

Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection

The RC-based power-rail ESD clamp circuit with the n-channel metal-oxide-semiconductor (NMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based ESD-transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions.

Improvement of lumen efficiency in white light-emitting diodes with air-gap embedded package

In this paper, white light-emitting diodes (LEDs) with air-gap embedded package were proposed and fabricated by a simple method including pulsed spray coating. The lumen efficiency of air-gap embedded LED was enhanced by 8.8% at driving current of 350 mA, compared to conventional remote phosphor white LED. This improvement was due to the enhanced utilization of blue and yellow rays, which were confirmed by pulse current-dependent correlated color temperature (CCT). The utilization efficiency of blue rays was enhanced by 12.4% due to the embedded air-gap layer. The simulation results performed by Monte-Carlo ray tracing method agreed with our experiments, which showed enhancement in lumen efficiency and similar CCT. Finally, the electric field intensity versus different thickness for air-gap and no air-gap embedded white LED was calculated to check the incident blue rays trapped in phosphor layer.

Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits

The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at radio-frequency (RF) front-end and high-speed input/output (I/O) pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes drawn in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The measured results confirmed that they can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the stripe and waffle diodes, especially for the diodes drawn in the hollow layout style. Therefore, the signal degradation of RF and high-speed transmission can be reduced because of smaller parasitic capacitance from the new proposed diodes.

High Area-Efficient ESD Clamp Circuit With Equivalent

A power-rail electrostatic discharge (ESD) clamp circuit realized with ESD clamp device drawn in the layout style of big field-effect transistor (BigFET), and with parasitic diode of BigFET as a part of ESD-transient detection mechanism, is proposed and verified in a 65-nm 1.2-V CMOS process. Skillfully utilizing the diode-connected MOS transistor as the equivalent large resistor and the parasitic reverse-biased diodes of BigFET as the equivalent capacitors, the new RC-based ESD-transient detection mechanism can be achieved without using an actual resistor and capacitor to significantly reduce the layout area by ~82%, as compared to the traditional RC-based ESD-transient detection circuit. From the measured results, the new proposed power-rail ESD clamp circuit with body effect of ESD clamp device can perform adjustable holding voltage under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on under fast power-on and transient noise conditions.

RC

CMOS technology has been widely used to produce many integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously increases the difficulty of electrostatic discharge (ESD) protection design. The power-rail ESD clamp circuit has been the key circuit to perform the whole-chip ESD protection scheme. Some ESD detection circuits were developed to trigger on ESD devices across the power rails to quickly discharge ESD current away from the internal circuits. Therefore, on-chip ESD protection circuits must be designed with the consideration of standby leakage to minimize the power consumption and the possibility of malfunction to normal circuit operation. The design of power-rail ESD clamp circuits with low standby leakage current and high efficiency of layout area in nanoscale CMOS technology is reviewed in this paper. The comparisons among those power-rail ESD clamp circuits are also discussed.

-Based Detection Mechanism in a 65-nm CMOS Process

An ultralow-leakage power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide devices and with silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit, the proposed power-rail ESD clamp circuit can achieve an ultralow standby leakage current. In addition, the ESD-transient detection circuit can be totally embedded in the SCR device by modifying the layout structure. From the measured results, the proposed power-rail ESD clamp circuit with an SCR width of 45 μm can achieve 7-kV human-body-model and 350-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current in the order of nanoamperes at room temperature under the normal circuit operating condition with 1-V bias.

On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology

A resistor-less power-rail electrostatic discharge (ESD) clamp circuit realized with only thin-gate-oxide devices and with a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By skillfully utilizing the gate leakage current to realize the equivalent resistor in the ESD-transient detection circuit, the RC-based ESD detection mechanism can be achieved without using an actual resistor to significantly reduce the layout area in I/O cells. From the measured results, the new proposed power-rail ESD clamp circuit with an SCR width of 45 μm can achieve 5-kV human-body-model and 400-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current of 1.43 nA at room temperature under the normal circuit operating condition with 1-V bias.

Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology

In this work, a new design of the ESD-transient detection circuit with the n-channel metal-oxide-semiconductor (nMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been proposed and verified in a 65nm 1.2V CMOS process. As compared to the traditional RC-based ESD-transient detection circuit, the layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long turn-on duration under the ESD stress condition, as well as better immunity against mis-trigger or transient-induced latch-on event under the fast power-on and transient noise conditions.

Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology

White light-emitting diodes with air-gap embedded package were proposed and fabricated through a simple method including pulsed spray coating. The lumen efficiency of air-gap embedded LED was enhanced by 8.8% compared to reference remote-phosphor LED.

Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events

The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at GHz RF and high-speed I/O pads in CMOS integrated circuits (ICs) due to the small parasitic loading effect and high ESD robustness. Based on waffle layout style, two modified layout styles have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the figures of merit (FOMs) of ESD protection diodes with new proposed layout styles can be successfully improved.