Hui-Wen Tsai

Improvement of lumen efficiency in white light-emitting diodes with air-gap embedded package

In this paper, white light-emitting diodes (LEDs) with air-gap embedded package were proposed and fabricated by a simple method including pulsed spray coating. The lumen efficiency of air-gap embedded LED was enhanced by 8.8% at driving current of 350 mA, compared to conventional remote phosphor white LED. This improvement was due to the enhanced utilization of blue and yellow rays, which were confirmed by pulse current-dependent correlated color temperature (CCT). The utilization efficiency of blue rays was enhanced by 12.4% due to the embedded air-gap layer. The simulation results performed by Monte-Carlo ray tracing method agreed with our experiments, which showed enhancement in lumen efficiency and similar CCT. Finally, the electric field intensity versus different thickness for air-gap and no air-gap embedded white LED was calculated to check the incident blue rays trapped in phosphor layer.

Effect of the Thermal Characteristics of Phosphor for the Conformal and Remote Structures in White Light-Emitting Diodes

The influence of the thermal effect of phosphor for conformal and remote structures in white light-emitting diodes was investigated using the junction and phosphor temperatures. Comparing the measured temperatures with IR thermometer, the remote structure has a higher phosphor temperature than the conformal structure. This result indicates that the phosphor in the conformal structure has demonstrated superior conduction because of the high thermal conductivity in surrounding. Furthermore, thermal distribution in the simulation results has shown to have favorable agreement with the experimental results. Consequently, the lifetime measurement is shown to verify the results of the simulation and experiment for both structural types.

Design of charge pump circuit in low-voltage CMOS process with suppressed return-back leakage current

A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide overstress problem in low-voltage CMOS process. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage, which is better than the conventional charge pump circuit with the same pumping stages. By reducing the return-back leakage current and without suffering gate-oxide reliability problem, the new proposed charge pump circuit is suitable for the applications in low-voltage CMOS IC products.

Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits

This paper presented a practical industry case of electrical overstress (EOS) failure induced by the latchup test in high-voltage integrated circuits (ICs). By using proper layout modification and additional circuit, the unexpected EOS failure, which is caused by negative-current-triggered latchup test, can be successfully solved. The new design with proposed solutions has been verified in the 0.6-μm 40-V Bipolar CMOS DMOS (BCD) process to pass the test for at least 500-mA trigger current, which shows high negative-current-latch-up immunity without overstress damage, compared with the protection of only the guard ring. Such solutions can be adopted to implement high-voltage-applicable IC product to meet the industry requirement for the mass production of IC manufactures and applications.

Active Guard Ring to Improve Latch-Up Immunity

A new design concept named as active guard ring and related circuit implementation to improve the latch-up immunity of ICs are proposed. Using additional sensing circuit and active buffer to turn ON the electrostatic discharge (ESD) protection transistors, the large-dimensional ESD (or I/O) devices can provide or receive extra compensation current to the negative or positive current perturbation during the latch-up current test. The new proposed solution has been verified in 0.6-μm 5 V process to have much higher latch-up resistance compared with the conventional prevention method of guard ring in CMOS technology.

Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits

Proper layout and additional circuit solution have been proposed to solve the practical EOS failure induced by latchup test in an industry case of high-voltage integrated circuits (IC). The modified design has been implemented in 0.6-um 40-V BCD (Bipolar-CMOS-DMOS) process to successfully pass the 500-mA negative trigger current test. By eliminating overstress damages as happened in the prior work with only guard ring protection, the proposed solution can be adopted to implement high-voltage-applicable IC products which meet the requirement of industry applications with sufficient latchup immunity.

Improving the lumen efficiency by air-gap embedded package in white light-emitting diodes

White light-emitting diodes with air-gap embedded package were proposed and fabricated through a simple method including pulsed spray coating. The lumen efficiency of air-gap embedded LED was enhanced by 8.8% compared to reference remote-phosphor LED.

Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation

A new 2xVDD-tolerant mixed-voltage I/O buffer circuit, realized with only 1xVDD devices in deep-submicron CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been designed and fabricated in a 0.13-μm CMOS process with only 1.2-V devices to serve a 2.5-V/1.2-V mixed-voltage interface, without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by simulation and experimental results with operating speed up to 133 MHz for PCI-X compatible applications.

Improve latch-up immunity by circuit solution

A concept of active guard ring and its corresponding circuit solution to enhance the latch-up immunity of integrated circuits (IC) are proposed and verified in a 0.6-um 5-V CMOS process. By detecting the over-shooting/under-shooting trigger current during latchup current test (I-test), some compensation current generated from on-chip ESD PMOS or NMOS devices through special circuit design can effectively reduce the latchup trigger current that injecting into the core circuit blocks. Therefore, the latchup immunity of I-test with positive or negative trigger current applied at the I/O pins can be significantly improved.

Latch-Up Protection Design With Corresponding Complementary Current to Suppress the Effect of External Current Triggers

The robustness against latch-up in the integrated circuits can be improved by supporting complementary current at the pad under the latch-up current test (I-test). By inserting additional junctions to form parasitic bipolar sensors, the external trigger can be monitored, and the ESD protection devices can be applied to provide such current and decrease the related perturbation to the internal circuits. The proposed design and the previous work with a single guard ring have been fabricated in the same 0.5-μm 5-V process. The experimental results confirm the enhanced latch-up tolerance of this work and the practicability in the SOC era.