Chih-Yen Lo

SOC Test Architecture and Method for 3-D ICs

3-D integration provides another way to put more devices in a smaller footprint. However, it also introduces new challenges in testing. Flexible test architecture named test access control system for 3-D integrated circuits (TACS-3D) is proposed for 3-D integrated circuits (IC) testing. Integration of heterogeneous design-for-testability methods for logic, memory, and through-silicon via (TSV) testing further reduces the usage of test pins and TSVs. To highly reuse pre-bond test circuits in post-bond test, an innovative linking mechanism shares TSVs and test pins of the 3-D IC. No matter how many layers are there in the 3-D IC, a large portion of TSVs and test pins is reserved for data application. Therefore, smaller post-bond test time is expected. A test chip composed of a network security processor platform is taken as an example. Less than 0.4% test overhead increases in area and time between 2-D and 3-D cases. Compared with the instinctively direct access, TACS-3D reveals up to 54% test time improvement under the same TSV usage.

A network security processor design based on an integrated SOC design and test platform

In this paper we present a generic network security processor (NSP) design suitable for a wide range of security related protocols in wired or wireless network applications. Following the platform-based design methodology, we develop four specific platforms, i.e., architecture platform, EDA platform, design-for-testability (DFT) platform, and prototyping platform, for our NSP design. With these platforms, design of the NSP chip becomes more efficient and systematic. A prototype chip of the NSP has been implemented and fabricated with a 0.18 mum CMOS technology. The chip area is 5 mm times 5 mm (with 1M gates approximately), including I/O pads. The operating clock rate is 80 MHz. The best performance of the crypto-engines is 1.025 Gbps for AES, 1.652 Mbps for RSA, 125.9/157.65 Mbps for HMAC-SHA1/MD5, and 2.56 Gbps for random number generator. Comparison result shows that our NSP is efficient in terms of performance, flexibility and scalability

An FPGA-based test platform for analyzing data retention time distribution of DRAMs

Data retention time distribution of a dynamic random access memory (DRAM) has a heavy impact on its yield, power, and performance. Accurate and detailed information of data retention time distribution thus is very important for the DRAM designer and user. This paper proposes an FPGA-based test platform for analyzing the data retention time distribution of a DRAM. Based on the test platform, a test flow is also proposed to classify the DRAM cells with different data retention times with respect to different supply voltage and temperature. We have demonstrated the test platform and test flow using a Micron 2Gb DRAM.

An SOC test integration platform and its industrial realization

One of the major costs in system-on-chip (SOC) development is test cost, especially the cost related to test integration. Although there have been plenty of research works on individual topics about SOC testing, few of them took into account the practical integration issues. In this paper, we stress the practical SOC test integration issues, including real problems found in test scheduling, test IO reduction, timing of functional test, scan IO sharing, etc. A test scheduling method is proposed based on our test architecture and test access mechanism (TAM), considering IO resource constraints. Detailed scheduling further reduces the overall test time of the system chip. We also present a test wrapper architecture that supports the coexistence of scan test and functional test. The test integration platform has been applied to an industrial SOC case. The chip has been designed and fabricated. The measurement results justify the approach-simple and efficient, i.e., short test integration cost, short test time, and small area overhead.

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs

Dynamic random access memory (DRAM) is one key component in handheld devices. It typically consumes significant portion of the energy of the device even if the device is in standby mode due to the refresh requirement. This paper proposes a hybrid error-correcting code (ECC) and redundancy (HEAR) technique to reduce the refresh power of DRAMs in standby mode. The HEAR circuit consists of a Bose-Chaudhuri-Hocquenghem (BCH) module and an error-bit repair (EBR) module to raise the error correction capability and minimize the adverse effects caused by the ECC technique such that the refresh period can be effectively prolonged and considerable refresh power reduction can be achieved. Analysis results show that the proposed HEAR scheme can achieve 40~70% of energy saving for a 2Gb DDR3 DRAM in standby mode. The area cost of parity data and ECC circuit of HEAR scheme is only about 63 % and 53 % of that of the ECC-only, respectively.

A built-in self-test scheme for 3D RAMs

Three-dimensional (3D) random access memory (RAM) using through-silicon vias for inter-die interconnects has been considered as a new approach to overcome the memory wall. In this paper, we propose a built-in self-test (BIST) scheme for 3D RAMs. In the BIST scheme, a clock-domain-crossing-aware test pattern generator is proposed to cope with the clock-domain-crossing issue. An inter-die synchronization mechanism is also proposed to synchronize the BIST circuits in different dies. Furthermore, the BIST circuit provides the high-programmability feature to support the selection of RAMs in a die for testing such that it can support thermal management during the test. We design the proposed BIST scheme in a 3D IC with processor and RAM dies. Experimental results show that the area cost of the BIST circuit is very small. The area overhead of the BIST circuit for four 8192×64-bit RAMs in a die is only 0.45% using TSMC 90nm 1P9M CMOS process technology.

Test Integration for SOC Supporting Very Low-Cost Testers

To reduce test cost for SOC products, it is important to reduce the cost of testers. When using low-cost testers which have a limited test bandwidth to perform testing, Built-In- Self-Test (BIST) is necessary to reduce the data volume to be transmitted between the tester and the device-under-test (DUT). We enhance the SOC test integration tool, STEAC, so that it can support SOCs containing BISTed cores which are to be tested by low-cost testers. A test chip is implemented to verify the proposed technique. Experimental results show that the enhanced STEAC successfully works with the HOY wireless test system and other low-cost testers.

A hybrid built-in self-test scheme for DRAMs

This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.

Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs

Three-dimensional (3-D) integration using through-silicon-via (TSV) is an emerging technology for integrated circuit (IC) design. It has been used in DRAM die stacking extensively. However, yield remains a key issue for volume production of 3-D RAMs. In this paper, we present a point-to-point interconnection structure derived from bus and propose a fault tolerance interface scheme for TSVs and micro bumps to enhance their manufacturing yield in the 3-D RAMs. The interconnection structure is inherently redundant and thus can replace defective TSVs or micro bumps without using repair circuits. Global and local reconfiguration approaches are proposed which benefit distinct situations of the 3-D RAM. Analyses show that the proposed intra-channel reconfigurable interconnection scheme can improve the yield of the 3-D RAM effectively. Compared to the previous solution using an inter-channel reconfigurable interconnection scheme, the yield improvement can be as large as 23% which is very significant.

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.