Yung-Fa Chou

A built-in self-test scheme for the post-bond test of TSVs in 3D ICs

Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test TSVs of a 3D IC. The BIST scheme, arranging the TSVs into arrays similar to memory, has the features of low test/diagnosis time and low silicon area cost. Simulation results show that the area overhead of the BIST circuit implemented with 0.18µm CMOS technology for a 16×32 TSV array in which each TSV cell size is 45µm2 is 2.24%. Also, the BIST needs only 130 clock cycles to test the TSV array with stuck-at faults. In comparison with the IEEE 1500-based test approach, the BIST scheme can achieve 85.2% area cost and 93.6% test time reduction.

Performance Characterization of TSV in 3D IC via Sensitivity Analysis

In this paper, we propose a method that can characterize the propagation delays across the Through Silicon Vias (TSVs) in a 3D IC. We adopt the concept of the oscillation test, in which two TSVs are connected with some peripheral circuit to form an oscillation ring. Upon this foundation, we propose a technique called sensitivity analysis to further derive the propagation delay of each individual TSV participating in the oscillation ring – a distilling process. In this process, we perturb the strength of the two TSV drivers, and then measure their effects in terms of the change of the oscillation ring’s period. By some following analysis, the propagation delay of each TSV can be revealed. Monte-Carlo analysis of a typical TSV with 30% process variation on transistors shows that the characterization error of this method is only 2.1% with the standard deviation of 8.1%.

Detection of SRAM cell stability by lowering array supply voltage

In this paper, we discuss a design-for-test technique for the detection of cell stability in static random access memory (SRAM). The power supply to the memory array is isolated and independently accessible from an external terminal. By lowering the array supply voltage, the cell stability is degraded, making the defective cells susceptible to noises induced by read/write operations. On-silicon characterization result using 0.18 /spl mu/m CMOS technology is reported. It shows that the weak tailing bits in the statistical distribution can manifest themselves. The implementation of the test mode is inherently low-cost and can be combined with previously proposed methods for an improved detection capability.

Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias

3-D integration provides a means to overcome the difficulties in design and manufacturing of system-on-chip (SOC) and memory products. Introducing a short vertical interconnect, called through-silicon via (TSV), makes it feasible to repair and recycle bad dies by stacking. We propose a method to accomplish this using a dual-TSV hardwired switch (DTHS) in which the via-hole location is programmable. With the DTHS, we activate a spare and establish inter-die routing. The spare is nothing but a good part in another bad die. To be 3-D reparable, the design is partitioned into disjoint parts. The effort for the modification is minor in view of that a typical SOC is readily composed of modules with predefined functions and supply voltages. The DTHS is used: 1) to shut off power connections of both failed and unused parts; 2) to disconnect their signal paths; and 3) to redirect them to the selected good parts in the stacked dies. Despite the speed is degraded due to the extra load incurred by the DTHS, our simulation shows that the increase in delay time can be limited below 100 ps with an over-designed buffer which occupies 0.8% of the area of a 30 μm TSV, using a 65-nm CMOS process. The performance degradation turns out to be a necessary evil, since the increased height of the die stack leads to a thermal conductivity poorer than its 2-D counterpart. The 3-D patch die helps to shorten time-to-market and turn the irreparable dies profitable.

A Test Integration Methodology for 3D Integrated Circuits

The three-dimensional (3D) integration technology using through silicon via (TSV) provides many benefits over the 2D integration technology. Although many different manufacturing technologies for 3D integrated circuits (ICs) have been presented, some challenges should be overcome before the volume production of 3D ICs. One of the challenges is the testing of 3D ICs. This paper proposes test integration interfaces for controlling the design-for-test circuits in the dies of a 3D IC. The test integration interfaces can support the pre-bond, known-good stack, and post-bond tests. The minimum number of required test pads of the proposed test interface for pre-bond test using is only four. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing. Simulation results show that the area overhead of the proposed test interfaces for a 3D IC with two dies in which each die implements the function of ITC’99 b19 benchmark is only about 0.15%.

Small delay testing for TSVs in 3-D ICs

In this work, we present a robust small delay test scheme for through-silicon vias (TSVs) in a 3D IC. By changing the output inverters threshold of a TSV in a testable oscillation ring structure, we can approximate the propagation delay across that TSV, and thereby detecting a small delay fault. SPICE simulation reveals that this Variable Output Thresholding (VOT) technique is still effective even when there is significant process variation in detecting a slow TSV with some resistive open defect that may escape the traditional at-speed test.

Defect oriented fault analysis for SRAM

Fault analysis is an important step in establishing detailed fault models or subsequent diagnostics and debugging of a semiconductor memory product. We have performed defect injection in the memory cell array of an industrial SRAM circuit and analyzed the faulty behavior with respect to each defect injected. We found that although some of the defects can be mapped to existing fault models, there are many defects that result in unmodeled faults. Moreover, a defect may exhibit a different faulty behavior at a different location in the cell array. The voltage and temperature parameters can also change the faulty behavior. The simulation results show that almost all open and short defects lead to stuck-at faults, transition faults, and data retention faults.

In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis

In this paper, we propose a method and the required architecture for characterizing the propagation delays of the through Silicon vias (TSVs) in a 3-D IC. First of all, every two TSVs are paired up to form an oscillation ring with some peripheral circuits. Their joint performance can thus be measured roughly by the oscillation period of the ring. Next, we utilize a technique called sensitivity analysis to further derive the propagation delay of each individual TSV participating in an oscillation ring-a distilling process. In this process, we perturb the strength of the two TSV drivers, and then measure their effects in terms of the change of the oscillation rings period. By some following analysis, the propagation delay of each TSV can be revealed. On top of scheme, we also present an architecture that can activate the performance characterization process of each test unit - that consists of two TSVs - one at a time in a proper sequence. The area overhead is only 18.97 equivalent two-input NAND gate per TSV, by which one can gain the ability to profile the capacitances and the propagation delays of the TSVs on a 3-D IC.

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis

A parametric delay fault could arise in a through-silicon via (TSV) of a 3-D IC due to a manufacturing defect. Identification of such a fault is essential for fault diagnosis, yield-learning, and/or reliability screening. In this paper, we present an innovative design-for-testability technique called variable output thresholding. We discovered that by dynamically switching the output of a TSV from a normal inverter to a Schmitt-Trigger inverter, the parametric delay fault on the TSV can be characterized and detected. SPICE simulation reveals that this technique remains effective even when there is significant process variation. A scalable test infrastructure indicates that the test time is modest at only 17.2 ms for 1024 TSVs and 648.8 ms for 32768 TSVs when the test clock is running at 10 MHz.

An FPGA-based test platform for analyzing data retention time distribution of DRAMs

Data retention time distribution of a dynamic random access memory (DRAM) has a heavy impact on its yield, power, and performance. Accurate and detailed information of data retention time distribution thus is very important for the DRAM designer and user. This paper proposes an FPGA-based test platform for analyzing the data retention time distribution of a DRAM. Based on the test platform, a test flow is also proposed to classify the DRAM cells with different data retention times with respect to different supply voltage and temperature. We have demonstrated the test platform and test flow using a Micron 2Gb DRAM.