Chih-Yuan Chan

A 3.1–10.6 GHz Ultra-Wideband CMOS Low Noise Amplifier With Current-Reused Technique

A 3.1-10.6 GHz ultra-wideband (UWB) low noise amplifier (LNA) utilizing a current-reused technique and a simple high-pass input matching network is proposed. The implemented LNA presents a maximum power gain of 16dB, and a good input matching of 50Omega in the required band. An excellent noise figure (NF) of 3.1-6dB was obtained in the frequency range of 3.1-10.6GHz with a power dissipation of 11.9mW under a 1.8-V power supply. The proposed UWB LNA demonstrates the highest power gain and lowest NF among the published works in 0.18-mum CMOS technology

High current density InN∕AlN heterojunction field-effect transistor with a SiNx gate dielectric layer

InN∕AlN metal-insulator-semiconductor heterojunction field-effect transistors with a gate-modulated drain current and a clear pinch-off characteristic have been demonstrated. The devices were fabricated using high-quality InN (26nm)∕AlN (100nm) epifilms grown by plasma-assisted molecular-beam epitaxy on Si (111) substrates. The devices exhibited a current density higher than ∼530mA∕mm with a 5μm gate length. The pinch-off voltage was at ∼−7V with an associated drain leakage current less than 10μA∕mm. The observed high current density may be attributed to the high sheet carrier density due to the large spontaneous polarization difference between InN and AlN.

Wiring Effect Optimization in 65-nm Low-Power NMOS

This letter investigates the wiring effect on RF performance in advanced 65-nm low-power CMOS technology. New designs are proposed to minimize the parasitic resistances and capacitances associated with the interconnects in the transistor. Compared with the standard multifinger devices provided by the foundry, the device with the optimized wiring parasitic capacitances and resistances presents improvement up to ~ 21% for fT (increased from 89 to 108 GHz) and ~ 22% for f max (increased from 130 to 159 GHz), respectively. The extracted equivalent circuit model parameters indicate that the proposed approach can effectively minimize the parasitic effects leading to improved RF performance of the advanced MOSFETs.

Impacts of gate recess and passivation on AlGaN/GaN high electron mobility transistors

In this study, the impacts of gate recess and passivation on AlGaN/GaN high electron mobility transistors (HEMTs) were investigated. The trap-related characteristics were studied in detail by several different measurements including dc current– voltage, current collapse, gate lag, and flicker noise characterizations. With a Cl2/Ar-recessed gate, drain current collapse factors (� Imax )o f� 37:5 and � 6:9% were observed before and after SiN passivation. The gate lag measurements showed that the lagging phenomena almost disappear with SiN passivation for both Cl2- and Cl2/Ar-recessed devices. However, the flicker noise measurements revealed distinct noise levels of devices with different processes even after passivation. As the gate voltage (VG) changed from 2 to � 4 V, the devices recessed by Cl2 exhibited lower drain noise current densities (SID=ID 2 ranging from 2:8 � 10 � 14 to 1:7 � 10 � 12 Hz � 1 at 1 kHz) than those etched by Cl2/Ar mixture gas (SID=ID 2 ranging from 6:3 � 10 � 14 to 6:0 � 10 � 12 Hz � 1 at 1 kHz), whereas the devices without the recess process showed the lowest noise levels (SID=ID 2 ranging from 2:8 � 10 � 15 to 1:3 � 10 � 13 Hz � 1 at 1 kHz). It was found that SID=ID 2 increased monotonically when VG

Square-Gate AlGaN/GaN HEMTs With Improved Trap-Related Characteristics

In this brief, the trap-related characteristics of high-breakdown AlGaN/GaN high-electron-mobility transistors (HEMTs) were investigated. Compared with a conventional multifinger layout, the square-gate design presented reduced the current collapse from 19% to 6% and almost eliminated the gate lag. The flicker noise density and the gate leakage decreased from 1.16 times10^-10 to 1.17 times10^-11 1/Hz (<i>f</i> = 100 Hz) and from 7.36 times10^-5 to 1.80 times10^-6 A/mm ( <i>V</i> _GS = -4 V and <i>V</i> _DS = 100 V), respectively. The breakdown voltage was also improved from 350 to 650 V. With the channel area away from the defects generated by the mesa etching process, the square-gate AlGaN/GaN HEMTs demonstrated excellent performance with much less trapping effects.

Impact of STI Effect on Flicker Noise in 0.13-

This paper reports on the impact of shallow-trench isolation (STI) on flicker noise characteristics in 0.13-mum RF nMOSFETs. The drain noise current spectral density was measured in both triode and saturation regions for a more complete study. The devices with a relatively small finger width and a large finger number (W=1 mum/Nfinger=40 and W=5 mum/Nfinger=8) presented more pronounced generation-recombination (G-R) noise characteristics compared to those with W=10 mum/Nfinger=4. In addition, a wide noise level variation of more than one order of magnitude was associated with the more obvious G-R noise components. The observed trends can be explained by the nonuniform stress effect of STI and also the associated traps at the edge of the gate finger between STI and the active region. To further study the noise mechanism, the single-linger devices with different STI-to-gate distances [SA(SB)=0.6,1.2, and 10 mum] were investigated. The measured results provided a direct evidence of STI effect on flicker noise characteristics. The activation energy of the traps was extracted at various temperatures in a range from EC-0.397 to EC-0.54 eV. Moreover, the calculated standard deviation sigmadB showed a strong dependence of noise variation on device geometry (sigmadB=2.95 dB for W=1 mum/Nfinger=40 and sigmadB=1.54 dB for W=10 mum/Nfinger=4). The analysis suggests that the carrier number fluctuation model with the correlated mobility scattering is more suitable for the noise characteristics in these devices.

\mu \hbox{m}

This paper proposed a new device layout to improve the flicker noise and generation-recombination (G-R) noise characteristics in 0.13-μm RF N-MOSFETs. By extending the active region edge along the gate, the impact of stress and traps introduced by shallow trench isolation (STI) on device flicker noise was reduced significantly. Under a fixed V_DS of 1 V and V_GS of 0.5 V, the edge-extended devices (W/L= 1/0.13, N_finger= 40) present a reduced noise current spectral density (S_ID/I²) variation to only ˜ one third (S_ID/I² ranges from 4.5times10^-12 to 9.4times10^-12 Hz^-1 at 100 Hz) of that for devices with conventional layout (S_ID/I² ranges from 2.33times10^-12 to 1.69times10^-11 Hz^-1 at 100 Hz). The associated G-R bulges in flicker noise were almost disappeared with the new design. This study indicates the imperfections and stress at the STI edge are important origins to affect flicker noise characteristics especially for RF devices with a small finger width. In addition, the tradeoff between the improved flicker noise characteristics and the device RF performance is also investigated.

RF nMOSFETs

A fully integrated frequency divider with an operation frequency up to 20 GHz is designed in 0.18-mum CMOS technology. The frequency divider includes two stages to divide the input signal by a factor of 4. A wide locking range from 18.8 to 23.2 GHz was obtained with a low phase noise of -134.8 dBc/Hz (1-MHz offset) at an output frequency of 4.7 GHz. The first stage is designed by an analog methodology with the varactors to extend the locking range, while the second stage is designed by a digital approach with the RF devices for a high operation frequency. With the advantages of both designs, this frequency divider is operated at the frequency range suitable for LMDS applications.

Edge-extended Design for Improved Flicker Noise Characteristics in 0.13-μm RF NMOS

Impact of substrate noise coupling on a wideband VCO (5.6 to 7.5 GHz) was investigated using different noise injection topologies. Measured results indicated that IM2 increased by ~ 5 to 7 dB and IM3 by ~ 6 to 10 dB when the inductor guard ring floated. In addition, the noise at high frequencies still degraded the VCO performance even not injected directly to the substrate. The observed trends were modeled and explained by a simple physical-based resistive network together with the oxide layer capacitors successfully.

A Wide Locking-Range Frequency Divider for LMDS Applications

This paper reports the effect of shallow-trench-isolation (STI) on generation-recombination (G-R) noise and flicker noise variation in 0.13-μm RF MOSFETs for the first time. The devices with relatively small finger widths (W = 1 μm/Nfinger = 40 and W= 5 μm/Nfinger = 8) presented more pronounced G-R noise compared to those with W= 10 mum/Nfinger = 4 devices. In addition, a wide variation of noise levels was observed for devices with smaller finger widths and more finger numbers. The results can be explained by the effect of STI, which affects the carrier mobility due to the compressive stress, also generates traps at the edge of STI region resulting in G-R noise. Moreover, the metals employed in 0.13-μm CMOS technology, Cu and Co, may also be responsible for the G-R noise observed in the devices.