Jun-De Jin

A 3.1–10.6 GHz Ultra-Wideband CMOS Low Noise Amplifier With Current-Reused Technique

A 3.1-10.6 GHz ultra-wideband (UWB) low noise amplifier (LNA) utilizing a current-reused technique and a simple high-pass input matching network is proposed. The implemented LNA presents a maximum power gain of 16dB, and a good input matching of 50Omega in the required band. An excellent noise figure (NF) of 3.1-6dB was obtained in the frequency range of 3.1-10.6GHz with a power dissipation of 11.9mW under a 1.8-V power supply. The proposed UWB LNA demonstrates the highest power gain and lowest NF among the published works in 0.18-mum CMOS technology

A 40-Gb/s Transimpedance Amplifier in 0.18-

A 40-Gb/s transimpedance amplifier (TIA) is realized in 0.18-mum CMOS technology. From the measured S-parameters, a transimpedance gain of 51 dBOmega and a 3-dB bandwidth up to 30.5 GHz were observed. A bandwidth enhancement technique, pi-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of 1.17 X 0.46 mm2. The proposed CMOS TIA presents a gain-bandwidth product per DC power figure of merit (GBP/Pde) of 180.1 GHzOmega/mW.

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This study presents a high performance K-band low noise amplifier. By utilizing transformer feedback at the input stage, an excellent noise figure (NF) of 4.3 dB is obtained at 22 GHz. With the current-reused technique between the two stages, the amplifier achieves a maximum power gain of 10.1 dB under a supply voltage of 1.8 V and a power consumption of only 7.2 mW. The proposed LNA has comparable NF and gain, while it can operate under the lowest power among the published works in 0.18 mum CMOS technology for K-band applications.

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An ultra-low-power 60 GHz low-noise amplifier (LNA) with a 12.5 dB peak gain and a 5.4 dB minimum NF is demonstrated in a 90 nm CMOS technology. The LNA is composed of four cascaded common-source stages with the gate-source transformer feedback applied to the input stage for simultaneous noise and input matching. Also, the drain-source transformer feedback is used in the following stages for gain enhancement and interstage/output matching. This LNA consumes only 4.4 mW from a 1 V supply with a compact core area of 0.047 .

A Low-Power Low-Noise Amplifier for K-Band Applications

A six-stage transimpedance amplifier (TIA) was realized in a 0.18-mum complementary metal-oxide-semiconductor process. By adopting an effective gain-bandwidth product (GBW) enhancement technique, pi -type inductor peaking, the measured S 21, transimpedance gain, and bandwidth are 41 dB, 75 dBldrOmega, and 7.2 GHz, respectively, in the presence of an on-chip photodiode capacitance of 450 fF at the input. The 10-Gb/s TIA can operate under a maximum output swing of 800 mV pp and achieve a recorded GBW per DC power of 441.1 GHzldrOmega/mW.

An Ultra-Low-Power Transformer-Feedback 60 GHz Low-Noise Amplifier in 90 nm CMOS

A 70-GHz broadband amplifier is realized in a 0.13- mum CMOS technology. By using five cascaded common- source stages with the proposed asymmetric transformer peaking technique, the measured bandwidth and gain can reach 70.6 GHz and 10.3 dB under a power consumption (PDC) of 79.5 mW. Within the circuit bandwidth, the maximum input and output reflection coefficients are -6.1 and -10.8 dB, respectively. The group delay variation is plusmn 12.0 ps, and the output 1-dB compression point is 0.2 dBm at 5 GHz. With the miniaturized transformer design, the occupied core area of the circuit is only ~ 0.05 mm2 . This amplifier demonstrates a gain-bandwidth product of 231 GHz and a GBW/PDC up to 2.9 GHz/mW.

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Magnetic resonance components, including gradient coils and RF coils, are miniaturized using a MEMS batch fabrication process and are combined with a 0.18mum CMOS RF transceiver front-end to implement a compact imaging system. The system aims for a resolution of 6times6mum2 in a 120mum slice. The system could replace high-cost MRI counterparts for micron-resolution 3D images of live cells and enable a desktop cellular MRI system.

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The low-loss single semi-coaxial (S-SC) and differential semi-coaxial (D-SC) interconnects based on a standard 0.18-mum CMOS process are presented for the first time. Compared to the attenuation constant (alpha) reported for microstrip and CPW interconnects in CMOS process, the S-SC line shows the lowest loss of 0.90 dB/mm at 50 GHz. The D-SC line also presents a very low differential-mode alpha of ~1.00 dB/mm at high frequencies. The characteristics of D-SC lines for differential-mode and common-mode are also investigated in details based on the measured mixed-mode S-parameters

10-Gb/s Transimpedance Amplifier in 0.18-

A fully integrated frequency divider with an operation frequency up to 20 GHz is designed in 0.18-mum CMOS technology. The frequency divider includes two stages to divide the input signal by a factor of 4. A wide locking range from 18.8 to 23.2 GHz was obtained with a low phase noise of -134.8 dBc/Hz (1-MHz offset) at an output frequency of 4.7 GHz. The first stage is designed by an analog methodology with the varactors to extend the locking range, while the second stage is designed by a digital approach with the RF devices for a high operation frequency. With the advantages of both designs, this frequency divider is operated at the frequency range suitable for LMDS applications.

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Optical second harmonic generation (SHG) has been used to analyze the ULSI process, including low energy ion-implantation and rapid thermal annealing (RTA). The projected range of the low energy ion-implantation is approximately 20 nm, which results in a region that is transformed into an amorphous state by high dose ion-implantation, and the surface layer region is recrystallized during RTA process. The symmetrical point group of the Si (1 1 1) surface layer is 3 mm, which differs from that of centrosymmetric bulk Si which has no dipole contribution. The reflected SHG (RSHG) of the Si (1 1 1) is contributed mainly from the surface dipole and surface quadrupole. A plot of RSHG versus azimuthal angle reveals information on the recrystallization of amorphous silicon during RTA. The optimization of RTA step is determined by RSHG, which is shown to be suitable for analyzing the ULSI process.