Chihiro Matsui

Optimal memory configuration analysis in tri-hybrid solid-state drives with storage class memory and multi-level cell/triple-level cell NAND flash memory

This paper analyzes the best mix of memories in a tri-hybrid solid-state drive (SSD) with storage class memory (SCM) and multi-level cell (MLC)/triple-level cell (TLC) NAND flash memory. SCM is fast but its cost is high. Although MLC NAND flash memory is slow, it is more cost effective than SCM. For further cost efficiency, TLC NAND flash memory is denser and less expensive than MLC NAND flash. Performance of tri-hybrid SSD is evaluated in various memory configurations. Moreover, the optimum memory configuration is changed according to the application characteristics. If 10% cost increase is allowed compared to the MLC NAND flash only SSD, SCM/MLC NAND flash hybrid SSD provides the best performance with hot/random workload, whereas SCM/MLC/TLC NAND flash tri-hybrid SSD achieves the best for hot/sequential and cold/random workloads. In addition, it is possible to add long latency but low-cost SCM to the tri-hybrid SSD. As a result, tri-hybrid SSD with slow SCM achieves the best performance.

Design of Hybrid SSDs With Storage Class Memory and NAND Flash Memory

NAND flash memory-based solid-state drives (SSDs) are increasingly being used in both consumer and enterprise storage markets, due to their superior performance over hard disk drives (HDDs) and continuous bit cost reductions. With multiple-level cell technology memory device is capable of trading off the performance and endurance with bit density. The more bits per cell there are, the longer latency and shorter lifetime. On the other hand, the performance of such SSDs is limited due to NAND flash access speed as well as the need of garbage collection. Recently, storage class memories (SCMs) like resistive RAM (ReRAM) and phase change RAM (PRAM) have been developed to fill the bandwidth gap between DRAM and NAND flash memory. SCMs are nonvolatile and byte addressable, which are much faster and durable than NAND flash. Therefore, with SCMs, the storage performance would be significantly improved. Hybrid SSDs are promising cost-efficient storage solutions. Various types of memories like single-level cell (SLC), multiple-level cell (MLC), triple-level cell (TLC) NAND flash memories, and SCMs create lots of opportunities for new system architectures and algorithms. In this paper, the architecture and algorithm design overview of three types of hybrid drives including MLC/TLC NAND flash hybrid, SCM/MLC NAND flash hybrid, and SCM/MLC/TLC NAND flash tri-hybrid are presented. From the evaluation results, hybrid drives demonstrate better performance, endurance, and power consumption, compared to the MLC NAND flash only SSD. Furthermore, the relationship between device reliability and performance of the SCM/NAND flash hybrid SSD has been understood at a system level. There is a tradeoff between acceptable bit error rate of SCM and NAND flash. In addition, the decoding latency of SCM affects the performance of hybrid SSD more than that of NAND flash.

Optimal combinations of SCM characteristics and non-volatile cache algorithms for high-performance SCM/NAND flash hybrid SSD

In order to realize the high-performance solid-state drives (SSDs), SCM/NAND flash hybrid SSD has been proposed, which add Storage Class Memory (SCM) as a non-volatile cache to the NAND flash based SSD. This paper provides cache operation guidelines and the optimal SCM specifications for the hybrid SSD. Two algorithms, the hybrid SSD with 1) read-write cache and 2) write cache are discussed. SCMs are classified into two categories; memory-type SCM (M-SCM) and storage-type SCM (S-SCM). M-SCM is appropriate for hybrid SSD with write cache, while S-SCM is optimal for hybrid SSD with read-write cache. The impact of SCM read/write latency on the overall SSD performance is also analyzed. The required read/write latency of M-SCM and S-SCM are 0.1us/1us and 1us/3us, respectively to achieve 7-times higher performance compared with NAND flash based SSD. This means 10-times faster but one fourth smaller capacity M-SCM with write cache achieves the similar performance compared to S-SCM with read-write cache.

LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives

There is an increasing demand for the solid-state drive (SSD) due to its high speed, low power, and high reliability. However, random write intensive workload is not good for the SSD performance due to the inherent characteristics of the NAND flash memory. As the garbage collection (GC) causes the bottleneck of the SSD write performance due to the page-copy overhead, a NAND flash aware system is proposed to improve the SSD performance with a scheme called logical block address (LBA) scrambler. In the proposed scheme, new data are actively written to the fragmented pages in the next erase block. As a result, the number of valid pages inside the block is reduced when the block is recycled. Considering that there are NAND flash blocks full of valid pages in the proposed scheme, a skipping full block round robin (SFB_RR) GC policy is proposed, showing 0%-58% performance improvement compared with the RR GC policy. Furthermore, certain valid pages in the SSD have obsolete data due to the logical address remapping of the LBA scrambler, which cannot be invalidated by the conventional TRIM command, thus a SWEEP command is introduced. With the SWEEP command, maximum 12% additional SSD performance gain is obtained. From the experimental results, 35%-394% performance improvement, 27%-56% energy consumption reduction, and 25%-55% endurance enhancement are achieved by the proposed LBA scrambler scheme + SFB_RR GC policy + SWEEP command support, compared with the conventional SSD.

Write Order-Based Garbage Collection Scheme for an LBA Scrambler Integrated SSD

Solid-state drives (SSDs) are rapidly replacing hard disk drives in enterprise data centers due to their higher throughput and reliability. However, the SSD’s random write performance is limited by the NAND flash memories within the SSD, which require garbage collection (GC). To improve the write throughput, a logical block address (LBA) scrambler has been previously proposed. However, there are two issues associated with this solution. First, with the LBA scrambler, SSD throughput actually worsens for some types of workloads, such as prxy_0. Second, a large table size is needed. In this paper, the first problem is solved by a write order (WO)-based GC scheme. In order to choose the victim block, the parameters of valid page ratio, write order, and erase count of the NAND flash blocks are collectively considered according to a new formula. A key advantage of utilizing the relative write order of the blocks is that an internal timer is not needed to monitor the ages of the blocks. Second, a sector bundling scheme is proposed to reduce the table size of the LBA scrambler. Based on the experimental results, with the two proposals, SSD throughput is improved by 2.4 times, and the table size of the LBA scrambler is reduced by 45%.

Application dependency of 3-D integrated hybrid solid-state drive system with through-silicon via technology

Study of storage class memory (SCM) /NAND flash memory hybrid solid-state drive (SSD) is developed for enterprise storage system. The hybrid SSDs for enterprise applications require a large capacity. However, the larger hybrid SSD capacity becomes, the more energy is consumed. Then, through silicon-via (TSV) technology realizes to reduce energy consumption and footprint of the hybrid SSDs. In this paper, the energy consumption of three-dimensional (3-D) hybrid SSDs with the TSV are evaluated, and design guideline for the hybrid SSD system with the TSV is presented for application characteristics. From the evaluation results, the TSV is effective for the small-capacity low-end mobile hybrid SSD with the read-hot application, and 25.7% energy consumption reduction is obtained with the TSV. Additionally, the TSV is effective for the large-capacity high-end enterprise hybrid SSD with the read-cold application, and the energy consumption reduces by 56.6% with applying the TSV.

Real usage-based precise reliability test by extracting read/write/retention-mixed real-life access of NAND flash memory from system-level SSD emulator

Real usage-based precise reliability test for NAND flash of SSDs and reliability boost guidelines are proposed. Conventional simple reliability tests of data-retention and read-disturb cannot reproduce the real-life Vth shift and memory cell errors. The proposed reliability test method precisely reproduces the real memory cell failures by emulating the complicated read, write, and data-retention with SSD emulator. Based on the proposed reliability test, the guidelines of the read reference voltage shift are proposed to achieve the highest memory cell reliability for two kinds of real workloads.

Comprehensive analysis on SCM specifications for high-performance SCM/NAND flash hybrid SSD with through-silicon via

By adding SCM to NAND flash-based SSD, SCM/NAND flash hybrid SSDs have been proposed for performance improvement. This paper analyzes effects of SCM specifications such as read/write latency, capacity and I/O frequency on performance of the hybrid SSD with through-silicon via (TSV). From the evaluation results, TSV reduces energy consumption by 38% when the SCM capacity is 1% of the NAND flash capacity. In addition, the hybrid SSD achieves 2.1-times Input/Output per Second (IOPS) performance improvement compared with NAND flash-only SSD. The power consumption dependency of the SCM read/write latency and I/O frequency is also analyzed. Only SCM capacity affects the power consumption reduction by TSV. When the SCM capacity is 1% in the hybrid SSD, TSV reduces power consumption by up to 38%. In contrast to the result of power consumption, SCM capacity, read/write latency, and I/O frequency have a large effect on the IOPS performance. Up to 81-times IOPS performance is achieved when SCM capacity, latency, and I/O frequency are 10%, 100 ns, 4266 MHz, respectively.

22% Higher performance, 2x SCM write endurance heterogeneous storage with dual storage class memory and NAND flash

Storage class memories (SCMs); for instance, (STT-)MRAM, ReRAM, PRAM, and 3D XPoint, have much attention from storage systems. Each SCM has different characteristics, such as read/write latency, endurance, and bit cost. For example, MRAM has short latency and high endurance, but its cost is high. In contrast, ReRAM, PRAM, and 3D XPoint have lower endurance, but their cost is lower than MRAM. From these SCM characteristics, MRAM is classified into memory-type SCM (M-SCM), and ReRAM, PRAM, and 3D XPoint are called storage-type SCM (S-SCM). Previous studies show that SCM improves NAND flash based storage performance. However, cost of M-SCM is too high for storage usage. To bring out the best of M-SCM and S-SCM characteristics, this paper proposes a heterogeneous storage with two types of SCM, called dual SCM, and NAND flash memory. In the proposed storage, M-SCM stores very frequently accessed super-hot data and S-SCM stores hot data. By considering the storage performance and total storage cost, only 1% of M-SCM improves the storage performance by 22% and write endurance of S-SCM by 2 times compared with conventional S-SCM and NAND flash hybrid storage. With this storage configuration, M-SCM and S-SCM should have write cycles 3.2×102 and 4.5×101 times higher than MLC NAND flash.

3X Faster Speed Solid-State Drive with a Write Order Based Garbage Collection Scheme

Solid-state drives (SSDs) are over-taking hard disk drives (HDDs) as high-volume storage in enterprise servers and data centers. However, SSDs write performance is limited due to their inability to overwrite in-place and need for garbage collection. To reduce the garbage collection (GC) overhead, a logical block address (LBA) scrambler has been proposed. However, the LBA scrambler has two issues: (1) SSD performance decreases with a hot and random workload, and (2) the table size of the LBA scrambler may become upto 0.85% of the SSD capacity. In this work, a write order (WO) based GC scheme is proposed to solve the first issue. The number of valid pages in the NAND flash block, the write order and erase count of the block are considered for victim block selection during GC. One of the key advantages of the WO GC is that it does not require a clock inside the SSD, which will not operate if the SSD power is off. Further, to solve the second issue of the large table size, a Sector Bundling scheme is proposed. From the results, SSD performance is improved 3×, and the LBA scrambler table size is reduced 16%.