Atsuro Kobayashi

7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage

An enterprise-grade SSD with TLC (3b/cell) NAND Flash is presented with three techniques that achieve high speed and high reliability. Quick low-density parity-check (LDPC) reduces the read latency of 1Xnm TLC NAND Flash SSD by 83%. Dynamic VTH optimization and auto data recovery reduce the NAND Flash bit-error rate (BER) by 80% and 18%, respectively. These techniques can be implemented in the SSD controller without circuit overhead. No modification is required to the TLC NAND flash.

Versatile TLC NAND flash memory control to reduce read disturb errors by 85% and extend read cycles by 6.7-times of Read-Hot and Cold data for cloud data centers

Versatile Triple-Level-Cell (TLC) NAND flash memory control with Read Hot/Cold Migration, Read Voltage Control and Edge Word Line Protection is proposed for data center application SSDs. Measured errors decrease by 85% and measured acceptable read cycles increase by 6.7-times.

Flash Reliability Boost Huffman coding (FRBH): Co-optimization of data compression and V th distribution modulation to enhance data-retention time by over 2900x

Highly reliable data compression technique. Flash Reliability Boost Huffman coding (FRBH) is proposed for TLC NAND Flash memory. By decreasing the write data size and optimizing the memory cell Vth distribution at the same time, FRBH decreases data-retention errors by 92% and increases data-retention time by over 2900 times.

Real usage-based precise reliability test by extracting read/write/retention-mixed real-life access of NAND flash memory from system-level SSD emulator

Real usage-based precise reliability test for NAND flash of SSDs and reliability boost guidelines are proposed. Conventional simple reliability tests of data-retention and read-disturb cannot reproduce the real-life Vth shift and memory cell errors. The proposed reliability test method precisely reproduces the real memory cell failures by emulating the complicated read, write, and data-retention with SSD emulator. Based on the proposed reliability test, the guidelines of the read reference voltage shift are proposed to achieve the highest memory cell reliability for two kinds of real workloads.

Investigation of read disturb error in 1Ynm NAND flash memories for system level solution

Read-disturb characteristics in 1Ynm NAND flash memories have been investigated. The error regularity among word-lines is observed in 1Ynm (2nd generation below 20nm) triple-level cell (TLC) NAND flash. Consequently, unreliable page which exceeds error-correcting code (ECC) capability is occurred. To optimize ECC capability, system level solution with Bose-Chaudhuri-Hocquenghem (BCH) ECC is introduced. By adding parity bit to the unreliable pages for ECC calculation, a correctable bit-error rate (BER) can be increased by 1.3-times.

12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition

Value-Aware SSD with Vertical 3D-TLC (Triple-Level Cell) NAND flash for the image recognition is proposed to increase the acceptable bit-error rate (BER) by 12-times and extend the data-retention time by 300-times. In addition to the reliability improvement, the read time reduces by 26%. The proposed SSD combines new data-aware techniques with deep neural networks error tolerance. 10% BER of NAND flash is allowed while providing the accurate and fast image recognition. The design overhead in the SSD controller is negligibly small.

Quick-low-density parity check and dynamic threshold voltage optimization in 1X nm triple-level cell NAND flash memory with comprehensive analysis of endurance, retention-time, and temperature variation

NAND flash memorys reliability degrades with increasing endurance, retention-time and/or temperature. After a comprehensive evaluation of 1X nm triple-level cell (TLC) NAND flash, two highly reliable techniques are proposed. The first proposal, quick low-density parity check (Quick-LDPC), requires only one cell read in order to accurately estimate a bit-error rate (BER) that includes the effects of temperature, write and erase (W/E) cycles and retention-time. As a result, 83% read latency reduction is achieved compared to conventional AEP-LDPC. Also, W/E cycling is extended by 100% compared with conventional Bose–Chaudhuri–Hocquenghem (BCH) error-correcting code (ECC). The second proposal, dynamic threshold voltage optimization (DVO) has two parts, adaptive V Ref shift (AVS) and V TH space control (VSC). AVS reduces read error and latency by adaptively optimizing the reference voltage (V Ref) based on temperature, W/E cycles and retention-time. AVS stores the optimal V Refs in a table in order to enable one cell read. VSC further improves AVS by optimizing the voltage margins between V TH states. DVO reduces BER by 80%.