Ching-Lung Su

A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip

A dynamic quality-scalable H.264 video encoder is presented for power-adaptive video encoding. In 0.13mum CMOS technology, it requires 470kgates/13.3kB SRAM and consumes 7mW/183mW in encoding 30fps CIF/HD720 video. Compared to the state-of-the-art design for real-time HD720 video encoding, a 49% reduction in gate count and a 61% reduction in internal memory is achieved

A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications

This paper proposes a dynamic quality-adjustable H.264 baseline profile (BP) video encoder that comprises 470 Kgates and 13.3 kB SRAM in a core size of 4.3 × 4.3 mm2 using TSMC 0.13 ¿m 1P8M CMOS technology. Exploiting parameterized algorithms for motion estimation and intra prediction, the proposed design can dynamically configure the encoding modes with the design trade-off between power consumption and video quality for various video encoding applications. In addition, the proposed basic unit (BU)-based rate control hardware can maintain a constant and stable bit rate for network video transmission. It achieves real-time H.264 video encoding on CIF, D1, and HD720@30 frames/s with 7 mW to 25 mW, 27 mW to 162 mW, and 122 mW to 183 mW power dissipation in different quality modes.

A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing

In this paper we present a high throughput VLSI architecture design for context-based adaptive binary arithmetic decoding (CABAD) in MPEG-4 AVC/H.264. To speed-up the inherent sequential operations in CABAD, we break down the processing bottleneck by proposing a look-ahead codeword parsing technique on the segmenting context tables with cache registers, which averagely reduces up to 53% of cycle count. Based on a 0.18 mum CMOS technology, the proposed design outperforms the existing design by both reducing 40% of hardware cost and achieving about 1.6 times data throughput at the same time

Joint algorithm/code-level optimization of H.264 video decoder for mobile multimedia applications

In this paper, we propose a joint algorithm/code-level optimization scheme to make it feasible to perform real-time H.264/AVC video decoding software on ARM-based platform for mobile multimedia applications. In the algorithm-level optimization, we propose various techniques like fast interpolation scheme, zero-skipping technique for texture decoding, fast boundary strength decision for in-loop filtering, and pattern matching algorithm for CAVLD. In the code-level optimization, we propose the design techniques on minimizing memory access and branch times. The experimental result shows that we have reduced the complexity of H.264 video decoder up to 93% as compared to the reference software JM9.7. The optimized H.264 video decoder can achieve the QCIF@30Hz video decoding on an ARM9 processor when operating at 120MHz clock.

Low Complexity High Quality Fractional Motion Estimation Algorithm and Architecture Design for H.264/AVC

In this paper, we propose a low complexity high quality fractional motion estimation design for H.264/AVC. A mode reduction algorithm of sub-macroblock partitions reduces about 30% of the hardware cost for FME block matching. The algorithm provides the continuous search points in a modified search area to boost hardware utilization and own high feasibility for the VLSI array processing. Simulation results show that the proposed FME has 0.01196dB worse than and 0.0115dB better than JM9.3 at CIF and D1 formats, respectively. Moreover, an associated FME architecture with a configurable flexibility is also proposed in the paper. It adopts flexible mode selection between several sets of macroblock partitions for providing trade-off in computation complexity and video quality. According to the TSMC 0.13mum CMOS technology, the proposed design costs 112.7K gates with the maximum working frequency of 158 MHz. This design can realize the real-time H.264/AVC encoding on a D1 video and HD720 video at operation frequency of 40 MHz and 108 MHz, respectively

A H.264 basic-unit level rate control algorithm facilitating hardware realization

Rate control plays an important role for video coding especially in video streaming applications with bandwidth constraints. The inherent sequential processing in H.264 basic unit (BU) level rate control algorithm makes it hard to be realized in a pipelined H.264 hardware encoder without increasing the processing latency. In this paper we propose a new H.264 BU-level rate control algorithm facilitating hardware realization. The proposed algorithm breaks down the sequential processing dependence in the original rate control algorithm in JM and reduces 28% for QCIF, 66% for CIF, 87% for Dl of hardware cycles while maintaining good video quality. Simulation results shows that the proposed algorithm reduces MADs memory buffer size to be Nunit * 14bits, which amounts to 26% for QCIF, 59% for CIF, 83% for Dl reduction as compared to JM rate control. Moreover, the proposed algorithm possesses high feasibility for hardware realization.

A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC

In this paper, a low complexity high quality motion estimation architecture design was proposed for MPEG-4 AVC/H.264 video coding applications. The proposed design is based on a low complexity algorithm that reduces over 90% of complexity at the cost of 0.06968dB and 0.08296dB PSNR drop as compared to JM9.3 full search with a plusmn32 search range at CIF and D1 formats, respectively. Besides, the algorithm provides a capacity of scalable search range. We have also exploited an on-chip memory rotation scheme and a configurable summation of absolute difference processor to reduce the on-chip memory bandwidth and the hardware cost. According to the TSMC 0.18mum CMOS technology, the proposed design costs 47.9K gates, 4K bits of Cur./Ref. pixel buffer and 22 Kbits SRAM with the maximum working frequency of 125MHz. The proposed design can achieve realtime motion estimation on D1 video and HD720 video when operating at 40MHz and 105MHz, respectively

A multi-mode entropy decoder with a generic table partition strategy

In this paper a low cost and low power multi-mode entropy decoder is proposed. The proposed design is compatible to the entropy decoding for JPEG, MPEG-1/2/4, H.264 and VC-1 video coding standards. It adopts the code-word tables merging and sharing, and integrates the various entropy decoding into a single programmable design. To reduce the required memory space, a generic look-up table partition strategy covering various video coding standards is proposed. Besides, the low power concept of high probability data path with lower capacitance is also taken into account. The proposed multi-mode entropy decoder is implemented using TSMC 0.13 mum at the cost of 113,884 gates and 0.54 KB SRAM. Its maximum operating frequency achieves 166 MHz, which can support entropy decoding on high definition video larger than HD1080@48 fps.

A BU-based rate control design for H.264 and AVS video coding with ROI support

Rate control (RC) techniques play an important role for interactive video coding applications, especially in video streaming applications with bandwidth constraints. In this paper we propose a new BU-level rate control algorithm with ROI support and the associated architecture for H.264 and AVS by exploiting a new predictor model to predict the MAD value and target bits for hardware realization. The proposed algorithm breaks up the sequential processing dependence in the original H.264/AVS RC algorithm and reduces up to 80.6% of internal buffer size for D1 video encoding, while maintaining good video quality.

A dynamic quality-scalable H.264 video encoder chip

This paper proposes a dynamic quality-scalable H.264 video encoder that comprises 470Kgates and 13.3Kbytes SRAM using 1P8M 0.13μm CMOS technology. Exploiting parameterized algorithms for motion estimation and intra prediction, the proposed design can dynamically configure the encoding modes with the design trade-off between power consumption and video quality for various video encoding applications. It achieves real-time H.264 video encoding on CIF, D1, and HD720@30fps with 7mW-25mW, 27mW-162mW, and 122mW-183mW power dissipation in different quality modes.