Jiun-In Guo

A new chaotic key-based design for image encryption and decryption

In this paper, an image encryption/decryption algorithm and its VLSI architecture are proposed. According to a chaotic binary sequence, the gray level of each pixel is XORed or XNORed bit-by-bit to one of the two predetermined keys. Its features are as follows: (1) low computational complexity, (2) high security, and (3) no distortion. In order to implement the algorithm, its VLSI architecture with low hardware cost, high computing speed, and high hardware utilization efficiency is also designed. Moreover, the architecture of integrating the scheme with MPEG2 is proposed. Finally, simulation results are included to demonstrate its effectiveness.

A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding

The demand of high quality video and high data compression enables MPEG-4 AVC/H.264 to adopt the context-based adaptive variable length code (CAVLC) technique contrary to the traditional MPEG-4 VLC techniques. The paper presents a novel, low-cost, high-performance VLSI architecture design for MPEG-4 AVC/H.264 CAVLC decoding. We exploit five different techniques to reduce both the hardware cost and power consumption, and to increase the data throughput rate. They are PCCF (partial combinational component freezing), HLLT (hierarchical logic for look-up tables), ZTEBA (zero-left table elimination by arithmetic), IDS (interleaved double stacks), and ZCS (zero codeword skip). The proposed design can decode every syntax element per cycle. The synthesis result shows that the design achieves maximum speed at 175 MHz. When we synthesize the proposed design at the clock constraint of 125 MHz, the hardware cost is about 4720 gates under a 0.18 /spl mu/m CMOS technology, which achieves the real-time processing requirement for H.264 video decoding on HD1080i format video.

A new image encryption algorithm and its VLSI architecture

In this paper, a new image encryption algorithm and its VLSI architecture are proposed. Based on a defined bit recirculation function and a binary sequence generated from a chaotic system, the gray level of each pixel in the image is transformed. The features of the algorithm are as follows: 1) low computational complexity, 2) high security, and 3) no distortion. In order to implement the system, its VLSI architecture with low hardware complexity, high computing speed, and high feasibility for VLSI implementation is also designed. Finally, two encrypted images are simulated and the fractal dimensions of the original and encrypted images are computed to demonstrate the effectiveness of the proposed algorithm.

A New Array Architecture for Prime-Length Discrete Cosine Transform

A new approach to derive a systolic algorithm for primelength discrete cosine transform (DCT) is proposed. It makes use of the input/output (UO) data permutations and the symmetry property of cosine kernels such that the proposed array possesses outstanding E ( i A ) * = B,?. (4.2) performance in hardware cost of the processing elements (PE’s), average computation time, and the I/O cost. the asymptotic variances

A new k-winners-take-all neural network and its array architecture

In this paper, a new neural-network model called WINSTRON and its novel array architecture are proposed. Based on a competitive learning algorithm that is originated from the coarse-fine competition, WINSTRON can identify the k larger elements or the k smaller ones in a data set. We will then prove that WINSTRON converges to the correct state in any situation. In addition, the convergence rates of WINSTRON for three special data distributions will be derived. In order to realize WINSTRON, its array architecture with low hardware complexity and high computing speed is also detailed. Finally, simulation results are included to demonstrate its effectiveness and its advantages over three existing networks.

A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications

In this paper, a low-cost H.264/AVC video decoder design is presented for high definition television (HDTV) applications. Through optimization from algorithmic and architectural perspectives, the proposed design can achieve real-time H.264 video decoding on HD1080 video (1920 times 1088@30 Hz) when operating at 120 MHz with 320 mW power dissipation. Fabricated by using the TSMC one-poly six-metal 0.18 mum CMOS technology, the proposed design occupies 2.9times2.9 mm2 silicon area with the hardware complexity of 160K gates and 4.5K bytes of local memory

A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264

This paper proposes a high-performance direct two-dimensional transform coding IP design for MPEG-4 AVC/H.264 video coding standard. Because four kinds of 4 /spl times/ 4 transforms, i.e., forward, inverse, forward-Hadamard, and inverse-Hadamard transforms are required in a H.264 encoding system, a high-performance multitransform accelerator is inevitable to compute these transforms simultaneously for fitting real-time processing requirement. Accordingly, this paper proposes a direct 2-D transform algorithm which suitably arranges the data processing sequences adopted in row and column transforms of H.264 CODEC systems to finish the data transposition on-the-fly. The induced new transform architecture greatly increases the data processing rate up to 8 pixels/cycle. In addition, an interlaced I/O schedule is disclosed to balance the data I/O rate and the data processing rate of the proposed multitransform design when integrated with H.264 systems. Using a 0.18-/spl mu/m CMOS technology, the optimum operating clock frequency of the proposed multitransform design is 100 MHz which achieves 800 Mpixels/s data throughput rate with the cost of 6482 gates. This performance can achieve the real-time multitransform processing of digital cinema video (4096 /spl times/ 4 2048@30 Hz). When the data throughput rate per unit area is adopted as the comparison index in hardware efficiency, the proposed design is at least 1.94 times more efficient than the existing designs. Moreover, the proposed multitransform design can achieve HDTV 720p, 1080i, digital cinema video processing requirements by consuming only 0.58, 2.91, and 24.18 mW when operated at 22, 50, and 100 MHz with 0.7, 1.0, and 1.8 V power supplies, respectively.

A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications

A multi-standard (JPEG/MPEG-1/2/4/H.264) video decoder includes 252kgates and 4.9kB internal memory in a core size of 4.2times1.2mm 2 using 0.13mum 1P8M CMOS. The power consumption at 1.2V supply is 71 mW at 120MHz for real-time HD1080 and 7.9mW at 20MHz for real-time H.264 decoding of D1 video

A memory-efficient realization of cyclic convolution and its application to discrete cosine transform

This paper presents a memory-efficient approach to realize the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic (DA) computation, exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel, separate the kernel to be two perfect cyclic forms, and partition the content of ROM into groups to facilitate an efficient realization of a one-dimensional (1-D) N-point DCT kernel using (N-1)/2 adders or subtractors, one small ROM module, a barrel shifter, and ((N-1)/2)+1 accumulators. The proposed memory-efficient design technique is characterized by rearranging the content of the ROM using the conventional DA approach into several groups such that all the elements in a group can be accessed simultaneously in accumulating all the DCT outputs for increasing the ROM utilization. Considering an example using 16-bit coefficients, the proposed design can save more than 57% of the delay-area product, as compare with the existing DA-based designs in the case of the 1-D seven-point DCT. Finally, a 1-D DCT chip was implemented to illustrate the efficiency associated with the proposed approach.

Design and realization of a new signal security system for multimedia data transmission

We propose a new signal security system and its VLSI architecture for real-time multimedia data transmission applications. We first define two bit-circulation functions for one-dimensional binary array transformation. Then, we exploit a chaotic system in generating a binary sequence to control the bit-circulation functions defined for performing the successive transformation on the input data. Each eight-bit data elements is regarded as a set and is fed into an binary matrix being transformed on each row and each column of the matrix by these two bit-circulation functions such that the signal can be transformed into completely disordered data. The features of the proposed design include low computational complexity, regular operations suitable for low-cost VLSI implementation, high data security, and high feasibility for easy integration with commercial multimedia storage and transmission applications. We have performed Matlab simulation to verify the functional correctness of the proposed system. In implementing the system, a low-cost VLSI architecture has been designed, verified, and physically realized based on a 0.35m CMOS technology. The implementation results show that the proposed signal security system can achieve Mbytes/s data throughput rate that is fast enough for real-time data protection in multimedia transmission applications.