Ching-Wei Wu

A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low V MIN applications

A total solution for 8T dual-port (DP) SRAM to improve its operating voltage range (VMIN/VMAX) is proposed. Partial suppressed word-line (PSWL) technique improves the static noise margin (SNM) when both ports (A, B ports) access at the same time. Dummy read recovery (DRR) and negative bit-line (NBL) techniques are introduced to eliminate the dummy read induced write recovery failure and write contention failure, respectively. The silicon results show that the VDD operation window can be improved from 220mV to 570mV in 16nm FinFET technology.

A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS

This paper presents a configurable SRAM for low voltage operation supporting both pseudo two-port SRAM (P2P-SRAM) and single-port SRAM (SP-SRAM) functions in one compiler. Unlike conventional pseudo two-port SRAM that always performs read first, this work enables dynamic read-or-write-first selection and write-through function. It can improve SP-SRAM function speed by 90% faster than that of the conventional read-first pseudo two-port SRAM design. An area-free constant-negative-level write driver (CNL-WD), which is suitable for compiler development, is used to improve write Vmin for configuration range from 4 to 256 cells/BL. A testchip is fabricated in a 16nm Fin-FET CMOS technology with a 0.0907μm2 6T-SRAM cell.

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications

Mobile applications, such as smartphones streaming HD videos or virtual-reality headsets rendering 3D landscapes, need SRAM memories that can be put in a low-power state to extend battery life, but can also offer high performance operation when required [1]. This paper will merge a 10nm technology with a dual-rail SRAM architecture to achieve superior power savings and performance scaling in comparison to the previous 16nm technology node [2]. Due to its simple design and area efficient layout, the 6T SRAM bitcell continues to be the primary memory technology used in almost all SoC and processor designs in high volume manufacturing today. The 10nm technology uses low-leakage, high-performance, second-generation FinFET transistors; it also offers a 6T cell (0.042µm2), for area and power savings, that does not require read or write assist circuits to achieve low voltage (Vmin) operation. This bitcell uses a fin ratio of 1∶2∶2 (PU:PG:PD), as illustrated in Fig. 12.3.1.

A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS

1Mbit SRAM macro with adaptive leakage current reduction scheme is implemented in 28nm high-k metal gate CMOS technology. A current limiter that limits cell array leakage current at various process-voltage-temperature (PVT) corners is included in the proposed scheme. The leakage current is reduced by more than 60% at fast process corners by increasing virtual ground voltage (Vvgnd) while maintaining sufficient data retention margin. At low VDD or slow process corners, Vvgnd is lowered to maintain the data integrity in the bitcell.