Hung-jen Liao

A Large

Nanometer SRAM cannot achieve lower VDDmin due to read-disturb, half-select disturb and write failure. This paper demonstrates quantitative performance advantages of a zigzag 8T-SRAM (Z8T) cell over the decoupled single-ended sensing 8T-SRAM (DS8T) with write-back schemes, which was previously recognized as the most area-efficient cell under large σVTH/VDD conditions. Since Z8T uses only 1T for each decoupled read-port, faster 2T differential sensing (D2S) can be implemented within the same area as the single-ended DS8T. Thanks to D2S, Z8T cell enables much faster R/W speed at VDDmin than DS8T. For the same VDDmin/speed, Z8T reduces the cell area by 15%. The Z8T 32 Kb macro is 14% smaller area and 53% faster than DS8T cells. Three macros were fabricated using foundry provided 65 nm low-power and 90 nm generic processes. The measured VDDmin for a 65 nm 256-row 32 Kb and a 32-row 4 Kb macro are 430 mV and 250 mV respectively. The measured VDDmin for a 90 nm 256-row 64 Kb macro is 230 mV.

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This paper presents circuit techniques to improve write and read capability for dual-port SRAM design fabricated in a 45nm low-power process. The write capability is enhanced by negative write biasing without any reduction in the cell current for the other port. The result shows 12% better improvement with just 1.9% area overhead. This technique has been verified successfully on 65nm and 45nm SRAM chip and improved 120mV lower at 95% yield of minimum operation voltage than a conventional one. The read capability is enhanced by cell current boosting and word line voltage lowering schemes. The SNM is also enhanced significantly. The target is to work below 0.8V with the worst process corner variation.

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Due to global and local process variations, on-chip SRAM suffers failures at a low supply voltage (VDD). This study proposes a differential data-aware power-supplied D2 AP 8T SRAM cell to address the stability and trade-off-issues between write and half-select accesses that still remain in the conventional 8T and 6T cells. Powered by its bitline pair, the proposed 8T cell applies differential data-aware-supplied voltages to its cross-coupled inverters to increase both stability margins for write and half-select accesses. A boosted bitline scheme also improves the read cell current. Two 39 Kb SRAM macros, D2 AP-8T and conventional 8T, with the same peripheral circuits were fabricated on the same testchip with 45 nm and 40 nm processes. The measured VDDmin for the D2 AP-8T macro is 240 mV-200 mV lower than that of the conventional 8T macro across lots, wafers and dies.

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A 20nm high-κ metal-gate planar CMOS technology is optimized and developed for SoC platform applications that span a wide range of power and performance. This technology is based on a 20nm SoC process featuring high-κ metal gate and strain techniques for core logic transistors with low-power/high-performance and I/O transistors. A high-density and a high-performance embedded memory bit cell each has an area <;0.1μm2. This technology is targeted to high-density low-cost low-power high-performance applications, such as mobile applications with video. Increased threshold-voltage variation of scaled transistors reduces the static noise margin (SNM) and write margin (WM) of the SRAM bit cell. The effect is more predominant for the high-density SRAMs due to small device sizes and large memory capacity requirement for modern SoC design. Therefore, chip performance and minimum operating voltage (VDDmin) are both degraded by the embedded SRAM. Reducing the pass-gate strength or BL capacitance with slow WL rise are effective techniques to improve the SRAM cell stability [1,2]. Underdriving the pass-gate reduces the bit-cell read current but also reduces WM, resulting in SRAM performance degradation. Physically shortening the BL limits the SRAM array configuration. Lowering the SRAM cell power supply improves the WM [3,4], but is less effective than the negative-bitline-based write-assist technique. Compared to conventional techniques, this work presents a partially suppressed wordline (PSWL) scheme for read assist and a bitline-length-tracked negative-bitline-boosting (BT-NBL) scheme for write assist without significantly degrading SRAM performance. With the read/write assist circuitry, the overall VDDmin improvement is over 200mV in a 112Mb SRAM test-chip.

/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme

Decreasing read cell current (<i>I</i>_CELL) has become a major trend in nonvolatile memory (NVM). However, a reduced <i>I</i>_CELL leaves the operation of the sense amplifier (SAs) vulnerable to bitline (BL) level offset and SA input offset. Thus, small- <i>I</i>_CELL NVMs suffer from slow read speed or low read yield. In this study, we propose a new current-sampling-based SA (CSB-SA) to suppress the offset due to device mismatch, while maintaining tolerance for insufficient precharge time. These features enable CSB-SA to achieve a read speed 6.3 ×-8.1× faster than previous SAs, for sensing 100 nA <i>I</i>_CELLs on a 2 K-cell bitline. We fabricated a CMOS-logic-compatible, 90 nm, 512 Kb OTP macro, using the CSB-SA. This OTP macro achieves a random access time of 26 ns for reading sub-200 nA <i>I</i>_CELL. Measurements confirm that this 90 nm CSB-SA is also capable of sub-100 nA sensing.

A 45nm dual-port SRAM with write and read capability enhancement at low voltage

This paper demonstrates for the first time quantitative performance advantages of a zigzag 8T-SRAM (Z8T) cell over the decoupled single-ended sensing 8T-SRAM (DS8T) with write-back schemes, which was previously recognized as the most area-efficient cell under large σVTH/VDD conditions. Since Z8T uses only 1T for each decoupled read-port, faster 2T differential sensing (D2S) can be implemented within the same area as the single-ended DS8T. Thanks to D2S, Z8T cell enables much faster R/W speed at VDDmin than DS8T. For the same VDDmin/speed, Z8T save the cell area by 15%. A fabricated 256-row 32Kb Z8T SRAM, using a 65nm low-power process, is 14% smaller area and 53% faster than DS8T SRAM, and is 430mV lower VDDmin than 6T-SRAM. The 32-row 4Kb Z8T macro achieves 250mV VDDmin.

A Differential Data-Aware Power-Supplied (D

A 0.6 V 45 nm dual-rail SRAM design utilizing an adaptive voltage regulator targeting for an SRAM compiler application is proposed for the first time. The proposed work describes an adaptive mechanism to generate a cell-Vdd (CVDD), which tracks a certain voltage offset with respect to logic-Vdd (VDD), and provides a mean to lower the VDD down to 0.6 V. To relax IR-drop constraints of CVDD power routings in P&R flow, shifting bite-line (BL) pre-charge power supply from CVDD to VDD is adopted in this work. This also avoids the congestion of the VDD and CVDD power mesh. A 45 nm test chip has demonstrated that these concepts successfully can push the VDD_min down to 0.6 V, which is > 250 mV lower than the conventional single-rail SRAMpsilas.

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This paper proposes schemes for the direct measurement of bit-line (BL) voltage swing, sense amplifier (SA) offset voltage, and word-line (WL) pulse width, demonstrated in a 40 nm CMOS 32 kb fully functional SRAM macro with <;2% area penalty. This is the first such scheme to enable the optimal tuning of WL-pulse (WLP) width according to on-site measurement results for BL voltage swing, dynamic read stability, and write margin, all of which depend on WLP width. It also eliminates the need for additional margins related to BL voltage swing, which has conventionally been required to ensure adequate tolerances against simulation errors and inaccurate estimation of SA offset voltage. This opens up possibilities for a more aggressive approach to deal with WLP width instead of only ensuring the target BL voltage swing.

AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications

A long bitline precharge time in the write operation and a wide wordline pulse width in the read operation dominate the cycle time of large-capacity compilable SRAMs. A data-dependent bitline leakage current causes timing skew and erodes the sensing margin of conventional replica-column controlled embedded SRAM. A dual-mode self-timed (DMST) technique is proposed to generate two individual timing for the read and write operations, unlike in conventional SRAMs, in which they have the same control timing, to reduce the cycle time and power consumption of the SRAM. The RC delay on bitlines, variations in the write response time of a bitcell and data-dependent bitline leakage current are considered in the DMST. The DMST technique reduces the cycle time and the write active power consumption by 16%~30.7% and 15%~22.7%, respectively for a 65 nm 512 Kb SRAM.

A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-V MIN applications

Decreasing read cell current (ICELL) has become a key trend in nonvolatile memory (NVM). This is not only due to device size and VDD scaling while keeping the same threshold voltage (VTH), but also to the growing spread of the following applications: 1) multiple-level-cell (MLC) [1–2] to achieve smaller area-per-bit; 2) lower-VDD [3] to save power consumption; 3) Logic-process-compatible onetime programming memories (OTP) for embedding into mobile chips. A smaller ICELL leaves the sense amplifiers (SAs) operation vulnerable to 1) bitline (BL) level offset due to noise, bias and load (CBL) mismatches and 2) VTH variation. As device size and BL-pitch is continually scaled down, the above factors have become major showstopper for SAs. To tolerate these offsets, small-ICELLNVMs suffer from slow read speed or high read fail probability. Thus, a more largely offset tolerant SA is a prerequisite to achieve faster read speeds. In this study, we propose a new offset tolerant current-sampling-based SA (CSB-SA) to achieve 7× faster read speed than previous SAs for sensing small ICELL. A fabricated 90nm 512Kb OTP macro, using the CSB-SA and our CMOS-logic-compatible OTP cell [4], achieves 26ns macro random access time for reading sub-200nA ICELL. Measurements also confirmed that this 90nm CSB-SA could achieve sub-100nA sensing.