Ching-Yu Hung

Top-down design using cycle based simulation: an MPEG A/V decoder example

This paper presents a discussion of a top-down VLSI design approach which involves system level performance modeling, block level cycle based simulation, RTL/VHDL simulation and gate level emulation. An MPEG-2 audio/video decoder design example illustrates the use of this top-down approach. Most of the discussion concentrates on the concept of block level cycle based (BLCB) simulation. HW/SW co-design also played an important role in this work and our approach towards such co-design is discussed as well.

Performance modeling for system design: an MPEG A/V decoder example

This paper describes a system level performance simulation methodology for VLSI system design of complex signal processing devices. This methodology also provides a means for HW/SW co-simulation and co-design. An MPEG audio/video decoder example illustrates this approach. Through this example we demonstrate an extremely fast simulation method that can process multiple frames of MPEG-2 compressed video per minute, and provides the necessary information for developing and evaluating the decoder architecture. This also allows for rapid simulation over numerous test bitstreams. Our methodology allows us to measure many different performance metrics, quickly construct and alter the simulation model, process actual bitstreams, and generate test cases. A pathway for developing detailed simulation models of the lower levels of the design process is also discussed.