Dale E. Hocevar

A reduced complexity decoder architecture via layered decoding of LDPC codes

We apply layered belief propagation decoding to our previously devised irregular partitioned permutation LDPC codes. These codes have a construction that easily accommodates a layered decoding and we show that the decoding performance is improved by a factor of two in the number of iterations required. We show how our previous flexible decoding architecture can be adapted to facilitate layered decoding. This results in a significant reduction in the number of memory bits and memory instances required, in the range of 45-50%. The faster decoding speed means the decoder logic can also be reduced by nearly 50% to achieve the same throughput and error performance. In total, the overall decoder architecture can be reduced by nearly 50%.

Parametric yield optimization for MOS circuit blocks

Two techniques are presented for optimizing the parametric yield of digital MOS circuit blocks for VLSI designs. The first is based on quasi-Newton methods and utilizes the gradient of the yield. A novel technique for computing this yield gradient is derived and algorithms for its implementation are discussed. Geometrical considerations motivate the second method which formulates the problem in terms of a minimax problem. Both yield optimization techniques utilize transient sensitivity information from circuit simulations. Encouraging results have been obtained thus far; several circuit examples are included to demonstrate these techniques. >

Pattern-independent current estimation for reliability analysis of CMOS circuits

Accurate and efficient expected current is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, etc. A pattern-independent simulation approach for estimating this expected current waveform drawn by CMOS circuitry has been developed. Four original concepts are presented which allow an efficient and accurate estimation of expected current waveforms. They are: probability waveforms, probability waveform propagation, probabilistic circuit models, and statistical timing analysis. This approach is considerably faster than traditional methods and yields comparable results.<<ETX>>

Transient Sensitivity Computation for MOSFET Circuits

This paper discusses the algorithms and implementation necessary for computing time domain sensitivities during circuit simulation. The adjoint approach and the direct approach have been studied, and it was concluded that the direct approach is the best for implementation. The direct approach allows the transient sensitivities to be computed concurrently in time with the normal simulation, and it has been demonstrated that accurate sensitivity computations can be obtained, by simply allowing the sensitivity circuits to use the same time steps as the original circuit. This implementation also incorporates the charge based model for the MOSFETs and those sensitivity derivations are shown. It has been found that the responses of the sensitivity circuits can be discontinuous, and that this is due to discontinuities in the derivatives of the charge with respect to voltage. Derivations for various performance function sensitivities in terms of the response sensitivities are also given.

Efficient encoding for a family of quasi-cyclic LDPC codes

In general, encoding for LDPC codes can be difficult to realize efficiently. The paper presents techniques and architectures for LDPC encoding that are efficient and practical for a particular class of codes. These codes are the irregular partitioned permutation LDPC codes recently introduced by the author (Hocevar, D.E., Proc. IEEE Int. Conf. on Commun., p.2708-12, 2003). Since these codes are quasi-cyclic, it is known that a simpler encoding process does exist. The paper goes beyond that basic method by exploiting other structural properties to allow for a simpler and faster encoding process, in both software and hardware. Solutions for some rank deficient codes are also given.

Direct circuit simulation algorithms for parallel processing (VLSI)

The improvement in computational throughput of VLSI circuit simulation is addressed. A high degree of natural parallelism exists in the circuit simulation problem; potentially a large number of processor can be used efficiently. Three distinct approaches for obtaining parallel execution in direct-method circuit simulators are investigated. These approaches differ primarily in the size of the individual tasks used to obtain parallel execution. The relative advantages of each approach are examined, and performance data from simulations on parallel processing systems are presented. For the third approach, very good parallel efficiency was obtained; in some cases, 99% parallelism has been observed. >

An Extrapolated Yield Approximation Technique for Use in Yield Maximization

This paper is concerned with the computational problem of maximizing the yield of circuits. A statistical Monte Carlo based approach is taken in order to compute yield estimates directly and to decrease dimensionality dependence. The main contribution of this paper is a yield extrapolation technique which is very effective in maximizing the yield along a search direction. This technique is based upon a quadratic model of the circuit. Statistical yield estimates are computed from the model and correlated sampling is used to extrapolate along the search direction. Two simple methods for determining search directions are discussed and these are used to demonstrate the overall method through several examples.

Achieving flexibility in a Viterbi decoder DSP coprocessor

A Viterbi decoder hardware implementation suitable for wireless cellular applications is presented. This decoder is extremely flexible, both in the codes it handles, and in its system interface. Capabilities include multiple constraint lengths, multiple code rates, arbitrary frame size, puncturing and code polynomials. This paper discusses aspects of the implementation for which achieving this flexibility proved to be difficult. With a data throughput rate of 2.5 Mbps it is an ideal solution for 3rd generation base station architectures operating in conjunction with a DSP.

New implicit integration method for efficient latency exploitation in circuit simulation

To exploit time-domain latency in circuit simulation using direct methods, an accurate, computationally efficient model for slowly moving, dormant portions of the circuit is required. A new, implicit integration method, the overdetermined polynomial method (ODPM), has been developed which permits the formulation of an accurate latent model. Using the ODPM integration method, the Jacobian of a dormant subcircuit need not be reevaluated over a large number of time steps of varying size. An accurate Norton equivalent circuit that emulates the impedance and current characteristics of the subcircuit can be obtained without reevaluation of the Jacobian or nonlinear charge computations. This new approach for utilizing latency produces significant improvements in circuit simulation speed with no decrease in accuracy or generality. The authors have demonstrated speed gains of 3 to 20 times over TISPICE for several large circuits. >

Space-time codes with bit interleaving

We develop a new construction criterion for BSPK space-time codes. Based on this criterion, we propose a new method of improving the performance of space-time codes, namely bit interleaving. Then, we provide a computationally effective, iterative way of decoding bit interleaved space-time codes. At the end, we note the 2 dB gain due to the new approach. A proposed 16 state bit interleaved code operates close to 3 dB from the outage probability.