Chinmaya Mishra

Single Miller capacitor frequency compensation technique for low-power multistage amplifiers

Due to the rising demand for low-power portable battery-operated electronic devices, there is an increasing need for low-voltage low-power low-drop-out (LDO) regulators. This provides motivation for research on high-gain wide-bandwidth amplifiers driving large capacitive loads. These amplifiers serve as error amplifiers in low-voltage LDO regulators. Two low-power efficient three-stage amplifier topologies suitable for large capacitive load applications are introduced here: single Miller capacitor compensation (SMC) and single Miller capacitor feedforward compensation (SMFFC). Using a single Miller compensation capacitor in three-stage amplifiers can significantly reduce the total capacitor value, and therefore, the overall area of the amplifiers without influencing their stability. Pole-splitting and feedforward techniques are effectively combined to achieve better small-signal and large-signal performances. The 0.5-/spl mu/m CMOS amplifiers, SMC, and SMFFC driving a 25-k/spl Omega///120-pF load achieve 4.6-MHz and 9-MHz gain-bandwidth product, respectively, each dissipates less than 0.42 mW of power with a /spl plusmn/1-V power supply, and each occupies less than 0.02 mm/sup 2/ of silicon area.

An 11-Band 3–10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication

This work presents a receiver implementation for MB-OFDM UWB communication that enables 11 bands of operation covering 78% of the spectrum licensed by the FCC. First, important system-level considerations are discussed with basis on the specifications from the MB-OFDM standard. Next, the different circuit techniques employed in the implementation of the receiver are described. For the LNA design, a wideband impedance match network that takes into account the package components is introduced. A notch filter embedded in the LNA and its tuning mechanism are proposed to attenuate the interference from devices operating in the U-NII band from 5.15 to 5.35GHz. Based on the results of a recent investigation on frequency planning for MB-OFDM radios, a compact 11-band fast-hopping synthesizer implementation is proposed for the receiver. The 264-MHz baseband section consists of a linear phase low pass filter and a programmable gain amplifier; it presents an in-band group delay variation of less than 0.6 ns and 42 dB of gain in steps of 2 dB. The IC is fabricated in a 0.25-mum SiGe BiCMOS process, placed in a QFN package and mounted on FR-4 substrate for its characterization. Measurement results show a receiver gain of 78-67 dB and NF of 5-10 dB across the 11 bands from 3-10 GHz, while consuming 114 mA from a 2.5-V supply

Frequency planning and synthesizer architectures for multiband OFDM UWB radios

This work presents an analysis on frequency planning and synthesis for multiband (MB) orthogonal frequency-division multiplexing (OFDM) ultra-wideband (UWB) radios operating in the range of 3.1-10.6 GHz. The most important specifications for the frequency synthesizer in an MB-OFDM UWB transceiver are provided. A synthesizer architecture for an existing frequency plan is introduced along with a discussion on its performance and implementation. An alternative frequency plan and its corresponding synthesizer architecture are also proposed. It is shown how this modified frequency plan leads to a significant simplification in the synthesizer realization. The feasible performance of both synthesizer architectures is evaluated through macromodel simulations using realistic models for the building blocks. Finally, system-level simulation results showing the impact of synthesizer spurs on the bit error rate performance of an MB-OFDM UWB receiver in the presence of interferers are provided. The presented results and discussion provide valuable insight for the implementation of a 3.1-10.6-GHz UWB synthesizer.

A Continuous Time Multi-Bit

A third-order CT ΔΣ ADC that replaces the multi-bit quantizer and feedback DAC by a pulsewidth modulation (PWM) generator and time-to-digital converter (TDC) is implemented in 65 nm CMOS technology. The TDC provides a 50-level binary output code and a time-quantized feedback pulse to the modulator. It is shown that the TDC can achieve 11 bit linearity in time steps without calibration or dynamic element matching. The modulator achieves 68 dB DR in 20 MHz BW, consumes 10.5 m W and occupies 0.15 mm2.

\Delta \Sigma

Low-power, small-area, 20MHz-BW ADCs that can be integrated in nanoscale CMOS technologies are of immense interest to the wireless communication industry. Implementation of high-performance analog circuits in nanometric technologies faces several challenges [1]. Time-domain digital signal processing (TDSP) [2] can be used as an alternative for some analog circuits to overcome these challenges. The TDSP technique utilizes the high timing resolution available in nanoscale technologies, and can be implemented using digital circuits that are inherently less susceptible to noise. Circuits using this technique also become faster, smaller and consume less power with technology scaling. Hence, solutions using TDSP with as many digital circuits as possible are desired. An ADC architecture that uses a VCO-based time-domain quantizer is presented in [3]. This architecture uses a conventional feedback element (multi-element DAC with DEM) and 950MHz sample rate that leads to high power consumption. In this work, a pulse-width modulator (PWM) and an all-digital time-to-digital converter (TDC) are used to implement the quantizer as well as the feedback element in the time domain. This approach achieves the necessary linearity in the feedback path without DEM or calibration, and allows a low output rate of 250MS/s.

ADC Using Time Domain Quantizer and Feedback Element

This paper presents circuits based on Schottky barrier diodes (SBDs) in IBMs 0.13-mum SiGe BiCMOS process. Circuits such as sub-harmonic up-conversion mixers and frequency doublers are demonstrated at frequencies beyond 100 GHz on silicon. These circuits enable power generation at millimeter wave frequencies on silicon. The frequency doublers can deliver >0 dBm output power at 110 GHz and the 2X sub-harmonic up converters exhibit peak conversion loss of <3 dB up to 120 GHz.

A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element

A fast-switching carrier frequency generator for multi-band UWB radios is presented. It generates 11 carrier frequencies in quadrature in the range of 3.7-10GHz from a single frequency source. The architecture consists of a series of dividers, single sideband mixers with filtering and multiplexers. The IC is implemented in a 0.25mum SiGe BiCMOS technology and measured in a QFN package. With an active area of 2.2 times 1.9mm2 the system draws 75mA of current from a 3V supply

Silicon Schottky Diode Power Converters Beyond 100 GHz

This work presents two compensation techniques for low-voltage three-stage amplifiers driving large capacitive loads: single Miller capacitor compensation (SMC) and single Miller capacitor feedforward compensation (SMFFC). They are implemented in amplifiers fabricated in standard 0.5 /spl mu/m CMOS technology. The use of a single Miller compensation capacitor in three stage amplifiers is explored. The small compensation capacitors used in the proposed topologies enhance the bandwidth and significantly reduce the silicon area. Feedforward paths are properly used to improve the stability of the amplifiers. Experimental results show that the SMC and SMFFC amplifiers achieve gain-bandwidth products of 4.6 MHz and 9 MHz, respectively, when driving a load of 250 /spl Omega//120 pF. Each amplifier operates from a /spl plusmn/1 V supply, dissipates less than 0.42mW of power and occupies less than 0.02 mm/sup 2/ of silicon area.

A carrier frequency generator for multi-band UWB radios

An 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB is implemented in a 0.25mum BiCMOS process. It includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The packaged IC mounted on FR-4 substrate provides maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply

Single Miller capacitor compensated multistage amplifiers for large capacitive load applications

This paper presents the design, analysis, and experimental verification of a self-calibrating current-reused 2.4-GHz direct-modulation transmitter for short-range wireless applications. The key contributions are the design/analysis of a stacked power amplifier (PA)/voltage-controlled oscillator (VCO) architecture, the nonlinear frequency-dependent analysis of a Gilbert-cell-based root-mean-square detector, and an on-chip LC-tank calibration circuit that needs no analog-to-digital convertor (ADC)/digital signal processor. The stacked architecture reduces the number of required regulators, utilizes supply headroom effectively, and allows for an “ADC-less” calibration loop that can dynamically tune the PA center frequency by sensing the transmitted signal. The very nature of direct-modulation architecture obviates additional high-purity signal generators, reducing complexity and allowing online calibration. The system was implemented in TSMC 0.18 μm CMOS, occupies 0.7 mm2 (TX)+0.1 mm2 (self-tuning), and was measured in a QFN48 package on an FR4 PCB. Automatically correcting PA/VCO tank misalignment in this case yielded >4 dB increase in output power. With the automatic tuning active, the transmitter delivers a measured output power >0 dBm to a 100-Ω differential load, and the system consumes 22.9 mA from a 1.8-V core-circuit supply.