Jose Silva-Martinez

A frequency compensation scheme for LDO voltage regulators

A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capacitors for the load of LDO regulators, and improves transient response and noise performance. Test results from a prototype fabricated in AMI 0.5-/spl mu/m CMOS technology provide the most important parameters of the regulator viz., ground current, load regulation, line regulation, output noise, and start-up time.

A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors

A multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced. The compensation scheme uses the positive phase shift of left-half-plane (LHP) zeroes caused by the feedforward path to cancel the negative phase shift of poles to achieve a good phase margin. A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster. The amplifier bandwidth is not compromised by the absence of the traditional pole-splitting effect of Miller compensation, resulting in a high-gain wideband amplifier. The capacitors of a capacitive amplifier using the proposed techniques can be varied more than a decade without significant settling time degradation. Experimental results for a prototype fabricated in an AMI 0.5-/spl mu/m CMOS process show DC gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is /spl plusmn/1.25 V.

The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier

A recycling amplifier architecture based on the folded cascode transconductance amplifier is described. The proposed amplifier delivers an appreciably enhanced performance over that of the conventional folded. This is achieved by using previously idle devices in the signal path, which results in an enhanced transconductance, gain, and slew rate. Moreover, the input referred noise and offset analyses are included to demonstrate that the proposed modifications have no adverse effects on these design metrics. Transistor-level simulations and experimental results in TSMC 0.18 mum CMOS process confirm the theoretical results. When compared to the conventional folded cascode, and for the same area and power budgets, the proposed amplifier has almost twice the bandwidth (134.2 MHz versus 70.7 MHz) and better than twice the slew rate (94.1 V/mus versus 42.1 V/mus) while driving the same 5.6 pF load. Also a gain enhancement of 7.6 dB is observed.

A 60-dB dynamic-range CMOS sixth-order 2.4-Hz low-pass filter for medical applications

The design and implementation of a fully integrated complementary metal-oxide-semiconductor (CMOS) sixth-order 2.4 Hz low-pass fitter (LPF) for medical applications is presented. For the implementation of large-time constants both linearized operational transconductance amplifiers with reduced transconductance and impedance scalers schemes for grounded capacitors are employed. Experimental results for the filter have shown a dynamic range (DR) of 60 dB, while the harmonic distortion components are below -50 dB. The power consumption for the filter is below 10 /spl mu/W, the power supply is /spl plusmn/1.5 V, and the active area is 1 mm/sup 2/. The filter was fabricated in a double poly double metal 0.8 /spl mu/m CMOS process.

A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier

The design of a 2.4-GHz fully integrated /spl Sigma//spl Delta/ fractional-N frequency synthesizer in a 0.35-/spl mu/m CMOS process is presented. The design focuses on the prescaler and the loop filter, which are often the speed and the integration bottlenecks of the phase-locked loop (PLL), respectively. A 1.5-V 3-mW inherently glitch-free phase-switching prescaler is proposed. It is based on eight lower frequency 45/spl deg/-spaced phases and a reversed phase-switching sequence. The large integrating capacitor in the loop filter was integrated on chip via a simple capacitance multiplier that saves silicon area, consumes only 0.2 mW, and introduces negligible noise. The synthesizer has a 9.4% frequency tuning range from 2.23 to 2.45 GHz. It dissipates 16 mW and takes an active area of 0.35 mm/sup 2/ excluding the 0.5-mm/sup 2/ digital /spl Sigma//spl Delta/ modulator.

A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chip automatic tuning

A maximally flat 10.7-MHz fourth-order bandpass filter with an on-chip automatic tuning system is presented. The signal-to-in-band integrated noise ratio (SNR) of the automatically tuned filter is around 68 dB. The third intermodulation distortion (IM3) is lower than -40 dB for a two-tone input signal of 3.2 V peak to peak (V/sub p-p/). The complete system operates with supply voltages of +or-2.5 V. The power consumption of the system is 220 mW. All this has been achieved due to the use of a low-distortion transconductor, the development of a high-frequency CMOS resistor, and the realization of an advanced on-chip automatic tuning system for both frequency and bandwidth control. The chip has been fabricated in a standard 1.5- mu m n-well CMOS process. >

Transconductance amplifier structures with very small transconductances: a comparative design approach

A family of CMOS operational transconductance amplifiers (OTAs) has been designed for very small G/sub m/s (of the order of nanoamperes per volt) with transistors operating in moderate inversion. Several OTA design schemes such as conventional, using current division, floating-gate, and bulk-driven techniques are discussed. A detailed comparison has also been made among these schemes in terms of performance characteristics such as power consumption, active silicon area, and signal-to-noise ratio. The transconductance amplifiers have been fabricated in a 1.2-/spl mu/m n-well CMOS process and operate at a power supply of 2.7 V. Chip test results are in good agreement with theoretical results.

Low-voltage low-power LVDS drivers

Two low-voltage low-power LVDS drivers used for high-speed point-to-point links are discussed. While the previously reported LVDS drivers cannot operate with low-voltage supplies, the proposed double current sources (DCS) LVDS driver and the switchable current sources (SCS) LVDS driver are suitable for low-voltage applications. Although static current consumption is greater than the minimum amount required by the signal swing, the DCS LVDS driver is simple and fast. The SCS LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to previously reported realizations. Both drivers were fabricated in a standard 0.35-/spl mu/m CMOS process; they are compliant with LVDS standards and can operate at data rates up to gigabits-per-second.

A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector

A pseudo-differential fully balanced fully symmetric CMOS operational transconductance amplifier (OTA) architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. The OTA achieves a third harmonic distortion of -43 dB for 900 mV/sub pp/ at 30 MHz. The OTA, fabricated in 0.5-/spl mu/m CMOS process, is used to design a 100-MHz fourth-order linear phase filter. The measured filters group delay ripple is 3% for frequencies up to 100 MHz, and the measured dynamic range is 45 dB for a total harmonic distortion of -46 dB. The filter consumes 42.9 mW per complex pole pair while operating from a /spl plusmn/1.65-V power supply.

A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner

A high dynamic range RF variable gain amplifier (RFVGA) suitable for mobile digital television (DTV) tuners is presented. Variable gain is achieved using a capacitive attenuator and current-steering transconductance (Gm) stages, which provide high linearity with relatively low power consumption. A novel broadband input impedance matching scheme based on resistive shunt-feedback is proposed. This scheme allows the RFVGA to achieve a low noise figure. A gain control technique suitable for CMOS current-steering variable gain amplifiers is described; it features 1 dB per step resolution, independent of process and temperature variations. The chip is fabricated in six-metal 0.18mum CMOS technology and consumes 12.2mA current from 1.8V supply. The RFVGA achieves 16dB maximum gain, 33dB gain control range, a 4.3dB noise figure, and an IIP3 higher than 25dBm