Chip Weems

The Image Understanding Architecture

This paper provides an overview of the Image Understanding Architecture (IUA), a massively parallel, multilevel system for supporting real-time image understanding applications and research in knowledge-based computer vision. The design of the IUA is motivated by considering the architectural requirements for integrated real-time vision in terms of the type of processing element, control of processing, and communication between processing elements.The IUA integrates parallel processors operating simultaneously at three levels of computational granularity in a tightly coupled architecture. Each level of the IUA is a parallel processor that is distinctly different from the other two levels, designed to best meet the processing needs at each of the corresponding levels of abstraction in the interpretation process. Communication between levels takes place via parallel data and control paths. The processing elements within each level can also communicate with each other in parallel, via a different mechanism at each level that is designed to meet the specific communication needs of each level of abstraction.An associative processing paradigm has been utilized as the principle control mechanism at the low and intermediate levels. It provides a simple yet general means of managing massive parallelism, through rapid responses to queries involving partial matches of processor memory to broadcast values. This has been enhanced with hardware operations that provide for global broadcast, local compare, Some/None response, responder count, and single responder select. To demonstrate how the IUA may be used for vision processing, several sample algorithms and a typical interpretation scenario on the IUA are presented.We believe that the IUA represents a major step toward the development of a proper combination of integrated processing power, communication, and control required for real-time computer vision. A proof-of-concept prototype of 1/64th of the IUA is currently being constructed by the University of Massachusetts and Hughes Research Laboratories.

Iconic To Symbolic Processing Using A Content Addressable Array Parallel Processor

We discuss the design of a large scale Content Addressable Array Parallel Processor (CAAPP) for low, medium and high level vision processing. This new architecture combines associative processing with global broadcast and response to and from an array of cells, and array processing via local cellular square neighborhood computation. The capabilities of the CAAPP allow us to close the feedback loop between high level processing and low level processing by supporting communication between different representations of an image. The CAAPP would provide a means of mapping the signal level (iconic) pixel-based representation of an image into a symbolic intermediate level representation suitable for high level vision processing.