Chitranjan N. Reddy

Staggered pipeline access scheme for synchronous random access memory

Random access memory redundancy circuit employing fusible links

Timing control circuit for synchronous static random access memory

Reduced area word line driving circuit for random access memory

Dual-port random access memory having reduced architecture

Random access memory with fast, compact sensing and selection architecture

Random access memory having selective intra-bank fast activation of sense amplifiers

Burst random access memory employing sequenced banks of local tri-state drivers

Random access memory word line select circuit having rapid dynamic deselect

Highly integrated low voltage SRAM array with low resistance Vss lines