Kenneth A. Poteet

System including a data processor, a synchronous dram, a peripheral device, and a system clock

Apparatus and method for a memory unit with a processor integrated therein

Memory module arranged for data and parity bits

Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock

Staggered pipeline access scheme for synchronous random access memory

Random access memory redundancy circuit employing fusible links

Fuse selectable timing signals for internal signal generators

Timing control circuit for synchronous static random access memory

Reduced area word line driving circuit for random access memory

Process of making and a DRAM standby charge pump with oscillator having fuse selectable frequencies