Chong Gun Yu

A Quantum Definition of Threshold Voltage in MuGFETs

The dependence of threshold voltage on device dimensions and number of gates is analyzed. A new definition of threshold voltage, based on quantum-mechanical considerations, is proposed.

Drain breakdown voltage: A comparison between junctionless and inversion mode p-channel MOSFETs

A comparative study of the drain breakdown phenomena in junctionless (JL) and inversion mode (IM) p-channel MOSFETs has been investigated experimentally with different V GS , channel widths, and V SUB . In order to explain the dependence of drain breakdown voltages (BV DS ) on V GS , 3-D device simulation has been also performed. When the device is turned ON, the BV DS is larger in JL than IM transistors. The BV DS is decreased with the increase of |V GS | in IM transistors but it is increased in JL transistors. When the device is turned OFF, the BV DS is larger in IM than JL transistors. The BV DS is decreased with the increase of channel width for JL and IM transistors. The BV DS is decreased in IM transistor when the back surface state of Si film is changed from the accumulation to the inversion but it is almost constant in JL transistors.

New experimental findings on hot carrier effects in deep submicrometer surface channel PMOS

The correlation between gate current and substrate current in surface channel(SC) PMOS with effective channel length down to 0.15 /spl mu/m is investigated within the general framework of the lucky-electron model. It is found that the impact ionization rate increases, but the device degradation is not serious in deep submicrometer PMOS. To extend the lucky-electron model to deep submicrometer regime, we empirically model the effective pinch-off length as a function of the gate length and the gate bias voltage. SCIHE is suggested as the possible physical mechanism for the enhanced impact ionization and the gate current reduction.

Device Characterization and Design Guideline of Amorphous InGaZnO Junctionless Thin-Film Transistor

Amorphous InGaZnO junctionless thin-film transistors (a-IGZO JL-TFTs) with different active layer thicknesses and thermal treatments were fabricated. The unique feature of a-IGZO JL-TFTs is that all of the active layer and source/drain (S/D) electrodes are realized by the deposition of the InGaZnO thin film. A quantitative analysis to completely deplete the active layer when the device is turned OFF has been performed according to the active layer thickness. The impact of active layer thickness and thermal treatment on the performance of a-IGZO JL-TFTs has been investigated. With the increase in active layer thickness and annealing temperature, the transfer curves shifted to the negative direction. From the effects of S/D series resistance on the performance of a-IGZO JL-TFTs, the series resistance cannot be a serious problem when the contact size is small enough and the active layer is thick enough. To completely deplete the active layer, the impacts of the key device design parameters such as gate oxide thickness, gate workfunction, and high-

Effect of source and drain asymmetry on hot carrier degradation in vertical nanowire MOSFETs

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Effects of device layout on the drain breakdown voltages in MuGFETs

dielectrics on the device performance have been investigated using device simulation.

New Experimental Findings on Hot-Carrier-Induced Degradation in Lateral DMOS Transistors

Abstract Effects of source and drain (S/D) asymmetry on hot carrier degradation in vertical nanowire MOSFETs have been investigated with different nanowire radiuses. The S/D asymmetry causes different degree of hot carrier degradations between forward and reverse stresses. The actual stress voltage applied to the channel as a result of parasitic resistance and gate to junction overlap length is attributed to the cause of the asymmetric degradation. The narrower nanowire also suffers from worse hot carrier effects due to current crowding and geometric effects.

Nanowire width dependence of data retention and endurance characteristics in nanowire SONOS flash memory

Abstract The drain breakdown phenomena in n-channel MuGFETs have been investigated experimentally with different gate lengths, fin widths, fin numbers, and side surface orientations of fin body. In order to explain the dependence of drain breakdown voltage on physical parameters of MuGFETs, 3-D simulation has been also performed. The BV DS is decreased with the increase of fin width and fin numbers. It is clearly seen that the BV DS of devices with the 0° rotated fin body is larger than that of devices with the 45° rotated fin body. When the total fin width is constant, the observed results suggest that the optimum device layout considering BV DS in MuGFETs is the device structure with narrow fin and large fin numbers.

A comparative study on device degradation under a positive gate stress and hot carrier stress in InGaZnO thin film transistors

This paper presents new experimental findings on the hot-carrier-induced degradation in lateral DMOS with different gate oxide thickness and when it is stressed at elevated temperature. For thin oxide devices, the generation of interface states and the trapped holes are the causes of the reduction of IDS in the linear region and the increase of IDSAT in the saturation region, respectively. For thick oxide devices, the generation of interface states plays a dominant role for the reduction of IDS in both linear and saturation region. It is observed that the breakdown voltage of both thin and thick oxide devices is increased and the device degradation is reduced at elevated stress temperature.

A comparative study on hot carrier effects in inversion-mode and junctionless MuGFETs

Abstract The investigations on the nanowire width (W) dependence of memory performance including P/E (programming and erasing) speed, data retention time and endurance characteristics in nanowire SONOS flash memory have been performed through the measurement and the device simulation. From measured results, a narrow device has advantages in terms of a fast P/E speed and the endurance characteristics. However, a narrow device has disadvantage in terms of the decreased data retention time. Another disadvantage of a narrow device is expected to the large power consumption due to large GIDL (Gate Induced Drain Leakage) current. The device simulation was performed to explore the causes for a fast P/E speed, an enhanced endurance characteristics and the reduced data retention time in narrow devices.