Choong-Heui Chung

Oxide-silicon-oxide buffer structure for ultralow temperature polycrystalline silicon thin-film transistor on plastic substrate

A novel oxide-silicon-oxide buffer structure to prevent damage to a plastic substrate in an ultralow temperature (<120/spl deg/C) polycrystalline silicon thin-film transistor (ULTPS TFT) process is presented. Specifically, an amorphous silicon film was inserted as an absorption layer into buffer oxide films. The maximum endurable laser energy was increased from 200 to 800 mJ/cm/sup 2/. The fabricated ULTPS nMOS TFT showed a performance with mobility of 30 cm/sup 2//Vs.

Improvement in performance of transparent organic light-emitting diodes with increasing sputtering power in the deposition of indium tin oxide cathode

The performance of transparent organic light-emitting diodes (OLEDs) can be substantially improved by increasing the rf sputtering power in the deposition of an indium tin oxide cathode. This dependence of device performance on sputtering power is quite different from that reported for transparent OLEDs. The effect is attributed to sputtering induced substrate-heating resulting in chemical reactions at the Al–LiF–Alq3 interface and electron injection enhancement. By effectively dissipating the energy of sputtered particles, device damage can be taken away. The findings herein show that a transparent OLED having better electron injection properties than a conventional OLED can be fabricated.

High-performance ultralow-temperature polycrystalline silicon TFT using sequential lateral solidification

This letter presents technologies to fabricate ultralow-temperature (< 150 /spl deg/C) polycrystalline silicon thin-film transistor (ULTPS TFT). Sequential lateral solidification is used for crystallization of RF magnetron sputter deposited amorphous silicon films resulting in a high mobility polycrystalline silicon (poly-Si) film. The gate dielectric is composed of plasma oxidation and Al/sub 2/O/sub 3/ grown by plasma-enhanced atomic layer deposition. The breakdown field on the poly-Si film was above 6.3 MV/cm. The fabricated ULTPS TFT showed excellent performance with mobility of 114 cm/sup 2//V /spl middot/ s (nMOS) and 42 cm/sup 2//V /spl middot/ s (pMOS), on/off current ratio of 4.20 /spl times/ 10/sup 6/ (nMOS) and 5.7 /spl times/ 10/sup 5/ (pMOS), small V/sub th/ of 2.6 V (nMOS) and -3.7 V (pMOS), and swing of 0.73 V/dec (nMOS) and 0.83 V/dec (pMOS).

Excimer laser annealed poly-Si thin film transistor with self-aligned lightly doped drain structure

Abstract We have made an excimer laser annealed poly-Si thin film transistor (TFT). The stress of the poly-Si films crystallized by excimer laser annealing is studied by Raman spectroscopy. The transverse-optic phonon frequency is independent of the excimer laser energy, but dependant on the precursor a-Si film thickness. The nMOS TFT with a self-aligned lightly doped drain (LDD) structure shows low leakage current. The large leakage current of the pMOS TFT with non-LDD structure is reduced by the off-state stress. The gate to channel capacitance as a function of gate voltage for nMOS TFT shows the characteristic parallel shift of the capacitance–voltage curves with frequency variation.

Performance Improvement of Ultralow Temperature Polycrystalline Silicon TFT on Plastic Substrate by Plasma Oxidation of Polycrystalline Si Surface

The thin-film transistor (TFT) performances were enhanced and stabilized by the plasma oxidation of the polycrystalline Si surface prior to the plasma enhanced atomic layer deposition of an Al2O3 gate dielectric film. The authors attribute this improvement to the formation of a high-quality oxide interface layer between the gate dielectric film and the poly-Si film. The interface oxide has a predominant effect on the TFTs characteristics and is regulated by the plasma oxidation temperature and the gap distance between the electrode and polycrystalline Si surface

Plasma-free hydrogenation of ultralow-temperature polycrystalline silicon thin-film transistors with SiNx:H as interlayer dielectric

Plasma-free defect passivation is achieved on polycrystalline silicon thin-film transistors fabricated below 150°C by annealing and extracting H from SiNx:H interlayer dielectric. By annealing at 250°C without a plasma application, VT and μFE were improved from 11.5Vto3.5V and from 86cm2∕Vsto212cm2∕Vs, respectively. Improvement in performance is attributed to defect passivation by H diffusing out from SiNx:H. Dangling bonds and strained bonds can be acceptably passivated around 170°C, and 205°C, respectively. The activation energy for the diffusion of H into polycrystalline silicon was estimated to be 0.87eV.

Low-Voltage Operating Triode-Type Field Emission Displays Controlled by Amorphous-Silicon Thin-Film Transistors

Fully vacuum-sealed triode-type active-matrix field emission display (AMFED) having an active-matrix cathode on soda-lime glass substrate was designed and fabricated. Each pixel in the active-matrix cathode has the monolithically integrated structure of an amorphous–silicon thin-film transistor (a-Si TFT) and triode-type field emitter array with conical Mo-tips just on the drain of the a-Si TFT. Experimental data indicate that the emission currents of the fabricated active-matrix cathode could be successfully controlled by the a-Si TFT gate voltage. We demonstrated that an emitting image of a moving picture from the fully vacuum-sealed 2-inch AMFEDs could be achieved by switching the low bias-voltage of the a-Si TFT gate to a value below 25 V.

Self-aligned Thin Film Transistor Fabrication with an Ultra Low Temperature Polycrystalline Silicon Process on a Benzocyclobutene Planarized Stainless Steel Foil Substrate

Self-aligned p-channel thin film transistors (TFTs) were fabricated with an ultra low temperature polycrystalline silicon (poly-Si) process on benzocyclobutene planarized stainless steel foil substrates (SSFs). We have demonstrated a successful crystallization of large grain poly-Si films with sequential lateral solidification (SLS) method. The TFT performances were enhanced and stabilized by plasma oxidation of the polycrystalline Si surface prior to Al2O3 gate dielectric film, which was deposited by a plasma enhanced atomic layer deposition (PEALD) method. The fabricated TFT showed a field effect mobility of 95cm 2 /Vs, a threshold voltage of

Texture development and grain boundary faceting in an excimer laser-crystallized silicon thin film

A 50-nm-thick amorphous silicon film on a SiO2 substrate is crystallized by an excimer laser-induced sequential lateral solidification. In the crystallized film, the laser scanning direction has a tendency to generate the ⟨100⟩ texture formation, whereas the surface normal and another in-plane orientation (normal to the scanning direction), designated as rolling direction, do not reveal any distinct texture development. Some grain boundaries are faceted, suggesting having a low trap density. Thus, the presence of the faceted grain boundaries is favorable for polycrystalline silicon electronic devices, such as thin film transistors and solar cells. A further grain boundary faceting might be induced by annealing processes.

Planarization of Si Ridges in Sequential Lateral Solidification Process

The heights of ridges, which are formed after crystallizing amorphous Si films, vary linearly to the initial film thicknesses. Post laser treatments on ridges have an effect of leveling the heights of ridges and lead to improved thin-film transistor characteristics. Relevant parameters influencing the planarization process are discussed. The optimum energy for planarization corresponds to the energy at which ridge peak blunting is maximum.