Chouki Aktouf

Enhancing testability of system on chips using network management protocols

This paper shows how to adapt the P1500 design-for-test standard through network management protocols to make the testing problem of system-on-chips (SoCs) easier and cost-effective. For this purpose, a SoC is analyzed as a distributed system in which its own basic components or IP cores (intellectual properties) are considered as network agents according to SNMP (simple network management protocol) protocol. An experimental study was carried out to show the effectiveness of such an approach.

An Innovative Methodology for Scan Chain Insertion and Analysis at RTL

While raising the level of abstraction in design methodologies is uniformly accepted as desirable, raising Design For Test of complex VLSI chips is still challenging for both analysis and implementation. Still, testing logic can be described at the RT-level, and inserting it before synthesis has many advantages, among which the ability to debug testability issues early in the design flow, and leveraging the optimization done by the synthesis tool. But inserting DFT logic such as a full-scantest logic before synthesis brings its own challenges: the earlier it is inserted in the flow, the harder it is to provide low-overhead insertion. In this work, we combine the use of a lightweight synthesis with graph models for inferring logical proximity information from the design, and then use classic approximation algorithms for the traveling salesman problem to determine the scan-stitching ordering. We show how this procedure allows the decrease of the cost of both scan analysis and implementation, by measuring total wire length on placed and routed benchmark designs, both academic and industrial.

A graph-based approach to optimal scan chain stitching using RTL design descriptions

The scan chain insertion problem is one of the mandatory logic insertion design tasks. The scanning of designs is a very efficient way of improving their testability. But it does impact size and performance, depending on the stitching ordering of the scan chain. In this paper, we propose a graph-based approach to a stitching algorithm for automatic and optimal scan chain insertion at the RTL. Our method is divided into two main steps. The first one builds graph models for inferring logical proximity information from the design, and then the second one uses classic approximation algorithms for the traveling salesman problem to determine the best scan-stitching ordering. We show how this algorithm allows the decrease of the cost of both scan analysis and implementation, by measuring total wirelength on placed and routed benchmark designs, both academic and industrial.

A Global Optimization for Scan Chain Insertion at the RT-level

We present a new method for scan chain ordering specifically tailored for RTL-scan and its unique challenges.

Towards a Complete SNMP-Based Supervision of System-on-Chips

This work proposes an adaptation of classical network management protocols for the purpose of a deep testing and management of network-based electronic systems such as routers, switches, and personal computers. The basic idea of this work is to extrapolate the advantages of network management functions (monitoring, control, test…) to the level of an electronic device. To this end, the proposed approach starts very early in the design process of integrated circuits where the concept of managed integrated circuit is introduced. A widely known design-for-test (DFT) technique is extended to render it useful through classical TCP/IP networks. The suggested solution is described and its efficiency is illustrated through extensive experimentations.

Hardware-based network management framework for monitoring and testing of system-on-chips

This paper describes a way of monitoring and testing embedded cores within a System On a Chip (SoC) through classical network management protocols. All embedded cores can be tested and monitored through the hardware-based SNMP (Simple Network Management Protocol) proxy agent implemented within an SoC. The basic idea of this work is to extrapolate the advantages of network management functions (monitoring, control, test…) to the chip level. The proposed approach is described and its efficiency is illustrated through extensive experimentations.