Yann Kieffer

A multi-objective optimization for memory BIST sharing using a genetic algorithm

The memory BIST insertion involves the simultaneous optimization of several conflicting and competing objectives such as test time and power consumption during the test execution procedure. In this paper, a new memory BIST methodology is proposed which optimizes area overhead, test power and test time. It exploits Genetic Algorithms to find a set of Pareto optimal solutions. Since the designer is given a set of trade-off solutions between the three criteria, thus he can choose the most suitable one for his memory testing needs. The proposed algorithm is rigorously tested using several industrial designs.

A shared BIST optimization methodology for memory test

We present a methodology, based on genetic algorithms, that optimizes shared heterogeneous Memory BIST architectures with regards to area, testing peak power and test time.

Formulation and practical solution for the optimization of memory accesses in embedded vision systems

The design of embedded vision systems carries a difficult challenge regarding the access times of memories holding image data for some particular cases of image treatments. This paper studies the optimization challenge reflecting the efficient operation of adhoc memory systems proposed by electronic designers to alleviate this problem. New algorithms are proposed for producing solutions to this 3-objective problem, and numerical experiments are conducted on real-world data for validating their efficiency.

A Global Optimization for Scan Chain Insertion at the RT-level

We present a new method for scan chain ordering specifically tailored for RTL-scan and its unique challenges.

New techniques for selecting test frequencies for linear analog circuits

In this paper we show that the problem of minimizing the number of test frequencies necessary to detect all possible faults in a multi-frequency test approach for linear analog circuits can be modeled as a set covering problem. We will show in particular, that under some conditions on the considered faults, the coefficient matrix of the problem has the strong consecutive-ones property and hence the corresponding set covering problem can be solved in polynomial time. For an efficient solution of the problem, an interval graph formulation is also used and a polynomial algorithm using the interval graph structure is suggested. The optimization of test frequencies for a case-study biquadratic filter is presented for illustration purposes. Numerical simulations with a set of randomly generated problem instances demonstrate two different implementation approaches to solve the optimization problem very fast, with a good time complexity.

Efficient minimization of test frequencies for linear analog circuits

This paper proposes a new technique for the optimization of multi-frequency tests for linear analog circuits. Fault simulation is used to obtain the frequency intervals for the detection of each fault. New efficient algorithms are then presented for the selection of the optimal set of test frequencies within these intervals for the detection of all faults. Numerical simulations with randomly generated problem instances demonstrate the good time complexity of the proposed algorithms, with a large improvement over previous approaches (Mir et al 1996).

Meeting the Challenges of Optimized Memory Management in Embedded Vision Systems Using Operations Research

The ever growing complexity of signal and image processing applications, and the stringent constraints related to their implementation makes their design, simulation, and implementation more and more challenging. Memory management is among the main challenge that electronic designers have to face. In fact, it impacts heavily the main cost metrics, including area, performance (real-time aspect) and energy consumption, of modern-day electronic devices. For some particular cases of image treatments, with non-linear access patterns to the memory addresses, a co-designed architectural solution and its optimization process, called Memory Management Optimization (MMOpt), was proposed by Mancini et al. (Proc. DATE, 2012). It creates an ad-hoc memory hierarchy for accelerating the accesses to the memories holding large image data. This chapter studies the optimization challenge reflecting the efficient operation of the MMOpt tool, which is formalized as a 3-objective scheduling problem. New algorithms are proposed for producing efficient solutions, leading to enhance the run-time performance and reduce both energy consumption and cost of the circuits produced by MMOpt. The performance of these algorithms is compared, on the same real-world data set as used by Mancini et al. [14], against the one currently in use in the MMOpt tool. The results show that our algorithms perform well in terms of computational efficiency and solution quality.

Efficient algorithms for memory management in embedded vision systems

In the field of embedded vision systems, meeting the constraints on design criteria such as performance, area, and power consumption can be a real challenge. In fact, to alleviate the well known “Memory Mall”, it is mandatory to provide efficient memory hierarchies to reach usable performance for the system to be designed when it has to handle non-linear image treatments. To address this problematic, Mancini and Rousseau (Proc.DATE, 2012) have designed a software generator of memory hierarchies for each non-linear image operation. It allows one to improve dramatically the performance of the system, while moderately increasing its area and energy consumption. The trade-offs between these three parameters are then taken to the level of the design of the operation of this memory hierarchy, a problem that can be formalized as a 3-objective optimization problem. In this study, we formalize this problem and give new approaches both for the problem and particular sub-problems. The results on the same real-world data set as used by Mancini and Rousseau (Proc.DATE, 2012) show a very significant improvement and reduce the amount of transferred data up to 30% and a reduction of the computing time up to 15%.

Memory management in embedded vision systems: Optimization problems and solution methods

Embedded vision systems design faces a memory-wall kind of challenge: images are big, and therefore memories containing them have high latency; and still, high performance is desired. For the case of non-linear processings, Mancini and Rousseau (Proc. DATE 2012) have designed a software generator of adhoc memory hierarchies, called Memory Management Optimization (MMOpt). While the performance of the generated circuits is very good, design-time decisions have to be made regarding their operation in order to handle finely the compromise between the usual metrics of design area, energy consumption, and performance. This study tackles the optimization challenge set by the design of the operational behavior of the memory hierarchy generated by MMOpt. After a precise formulation as a 3-objective optimization problem is given, two algorithms are proposed, and their performance is analyzed on real-world processings against the previously proposed algorithms. The results show a reduction of the amount of transferred data by 17% on average, and of the computing times by 11.7%, for the same design area.

Applying Operations Research to Design for Test Insertion Problems

Enhancing electronic circuits with ad hoc testing circuitry—so-called Design for Test (DFT)—is a technique that enables one to thoroughly test circuits after production. But this insertion of new elements itself may sometimes be a challenge, for bad choices could lead to unacceptable degradations of features of the circuit, while good choices may help reduce testing costs and circuit production costs. This chapter demonstrates how methods from Operations Research—a scientific discipline rooted in both mathematics and computer science, leaning strongly on the formal modeling of optimization issues—help us adress such challenges and build efficient solutions leading to real-world solutions that may be integrated into electronic design software tools.