Chris C. Dao

Safety oriented automotive MCU power management

The new generation of Power Management Controller (PMC) for Microcontroller Units (MCU) in the automotive application field is targeting increased modularity and flexibility of use, aiming to simplify board design and reduce external components as well as to reduce both development time and high volume production cost. A structural PMC design approach is followed by breaking the Intellectual Property (IP) system into several fundamental building blocks. Each block has a well defined set of features to cover the most demanding applications but allowing for scalability and flexible use, and speed up overall system design. In this paper we present a scalable architecture for a 5V PMC in CMOS 55nm technology. It includes a novel bandgap voltage reference with high noise immunity and improved curvature trimming based on bipolar ratio, a set of Low Voltage Detectors (LVDs) working sequentially during rising/falling supply edges, High Voltage Detectors (HVD), and an auxiliary back-up 1.2V regulator able to support fast load transitions, while the main 1.2V regulator is dedicated to supply most of the power consumption. The PMC IP has been integrated in automotive MCUs, with area from 0.6 to 1.2mm2, and Si results indicate modular architecture provides excellent trade-off among system complexity, power, wide safety specification features, low risk, and time to market.

A versatile low-dropout voltage regulator for automotive applications

In an effort to build versatile automotive Micro Controller Units (MCUs), power management has been integrated into the last generation SoC, with the additional benefits of simplifying board design and lowering the cost of bill of materials. In this paper we present a novel architecture for a 5 V to 3.3 V linear voltage regulator which can operate in dual mode: regulator controller, when an external ballast transistor is present; regulator mode, when a compensating capacitor is present. The circuit is being fabricated in CMOS 55 nm technology with non volatile memory process extension, occupies 0.05 mm2, and dissipates 1 mA current plus load.